Detection circuit for detecting timing of two node signals

Details Detection circuit for detecting timing of two node signals Detection circuit for detecting timing of two node signals

2000-03-27

2001-11-13

Le, Vu A. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S194000, C365S210130

Reexamination Certificate

active

06317383

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to detection circuits for detecting the transition timings of two node signals, and more particularly relates to a circuit which is preferably used for a semiconductor memory which reads the content of a memory cell connected to a bit line by detecting, subsequent to charging of the bit line, using a sense-amplifier connected to the bit line, whether or not the bit line is discharged, which is a particularly common technology in the semiconductor memory field.
2. Description of the Related Art
Detection circuits for detecting the transition timing of two node signals have been demanded. For example, there is a circuit for detecting, after charging of a bit line, using a sense-amplifier connected to a bit line, whether or not the bit line is discharged, which is applied to a wide range of semiconductor memories, such as a ROM (read only memory), and a RAM (random access memory). In such semiconductor memories, since the number of the sense-amplifiers is smaller than the number of the bit lines due to the limitations of the specification or the layout, and the efficiency, one sense-amplifier is shared among a plurality of bit lines. Accordingly, a column selector is provided in each of the bit lines so that the sense-amplifier reads the content of the memory cell connected to a bit line selected by the column selector.
When, instead of an external signal, an internally generated signal controls the read operation of the content of the memory cell connected to the bit line, the timing of the charging completion of the bit line and the detection timing of the sense-amplifier must be detected. In order to do this, a dummy circuit having a construction equivalent to a memory circuit including a memory cell, a bit line, and a column selector provided in the bit line is provided in a semiconductor memory. Using the timing of the charging completion of the bit line and the detection timing of the sense-amplifier in the dummy circuit by causing the dummy circuit to simulate actions of the memory circuit is a common way to control the read operation of the content of a memory cell.
FIG. 4
shows the dummy circuit provided in a conventional semiconductor memory
400
. The semiconductor memory
400
includes a dummy circuit
40
having a memory cell
31
, a bit line
32
, a column selector
33
provided in the bit line
32
, and a sense-inverter
34
. The memory cell
31
is provided at the node formed by a word line
1
and the bit line
32
, which are components of the semiconductor memory
400
.
In the dummy circuit
40
, a reading operation of the content stored in a memory cell
31
of a memory circuit is simulated. In this simulated operation, the column selector
33
is switched on, and then the bit line
32
, which is connected to an input of the sense-inverter
34
, is precharged by a precharge-circuit (not shown). The electric potential of the bit line
32
increases due to the precharging. Accordingly, the input of the sense-inverter
34
becomes HIGH and the output thereof becomes LOW. The timing when the output of sense-inverter
34
becomes LOW is detected as the timing of the charging completion of the bit line
32
.
When the word line
1
becomes HIGH, since the memory cell
31
is switched on, the electric charge of the bit line
32
flows via the memory cell
31
to a ground GND. Accordingly, the bit line
32
is discharged, which, via the column selector
33
, causes the input of the sense-inverter
34
to be LOW and the output thereof to be HIGH. The timing when the output of the sense-inverter
34
becomes HIGH is detected as the detection timing of the sense-amplifier. Thus, the reading operation of the content stored in the memory cell is controlled by being triggered by those detection timings.
However, when the reading operation of the content stored in the memory cell is controlled by being triggered by the timing of the charging completion of the bit line
32
and the detection timing of the sense-amplifier in the dummy circuit
40
, the following problems are encountered.
As shown in
FIG. 4
, the bit line
32
is divided into two bit line segments
32
a
and
32
b
by the column selector
33
. Since the bit line segment
32
b
is connected to the memory cell
31
as well as a plurality of other memory cells, the load capacitance of junctions of the bit line segment
32
b
is larger than the load capacitance of the bit line segment
32
a
which is connected to the sense inverter
34
. Therefore, the timings of the rising edge and the falling edge of a bit line signal of the bit line segment
32
a
are different from those of the bit line signal of the bit line segment
32
b
. The timing differences will be described with reference to
FIGS. 4 and 5
.
FIG. 5
shows bit line signals of the bit line segments and signals generated based on the bit line signals.
In
FIG. 5
, a bit line signal A of the bit line segment
32
a
is input to the sense-inverter
34
, a bit line signal B of the bit line segment
32
b
is input to the column selector
33
, and an output signal C is output from the sense-inverter
34
.
Since the load capacitance of the junctions of the bit line segment
32
b
is larger than that of the bit line segment
32
a
, in the event of precharging, the bit line segment
32
b
is not fully charged thus having a low electric potential, whereas the bit line segment
32
a
is already fully charged thus having a high electric potential. As shown in
FIG. 5
, the timing of the rising edge of the bit line signal B occurs later than that of the bit line signal A. Therefore, when the timing of the charging completion of the bit line
32
is detected at the rising edge of the bit line signal A, in other words, at the falling edge of the output signal C from the sense-inverter
34
, although the bit line
32
is not fully charged, the timing of the charging completion of the bit line
32
is detected, which may lead to malfunctioning of the dummy circuit.
On the other hand, when the timing of the charging completion of the bit line
32
and the detection timing of the sense-amplifier is detected at the rising edge and the falling edge of the bit line signal B, respectively, there is no problem of detecting the timing of the charging completion of the bit line
32
at the rising edge of the bit line signal B. However, since the electric charge of the bit line segment
32
b
is discharged faster than that of the bit line segment
32
a
, when the memory cell
31
is switched on and the detection timing of the sense-amplifier is detected at the falling edge of the bit line signal B, the detection timing of the sense-amplifier is detected before the bit line signal A becomes LOW, in other words, before the level of an input signal to the sense-amplifier is determined, which may also lead to malfunctioning of the dummy circuit.
In order to prevent such malfunctioning, a dummy circuit having a flip-flop provided in a semiconductor memory is proposed. In this dummy circuit, a signal D shown in
FIG. 5
is generated as described below.
FIG. 6
shows a flip-flop
60
provided in the dummy circuit of a conventional semiconductor memory.
A data terminal D of the flip-flop
60
is connected to a power supply V
DD
. The bit line signals B and A are input to a clock terminal CK and a clear terminal CL of the flip-flop
60
, respectively.
When a HIGH bit line signal A is input to the clear terminal CL of the flip-flop
60
and the bit line signal B changes from LOW to HIGH, since a HIGH signal is input from the power supply V
DD
to the data terminal D, a LOW signal D is output from an inverted output terminal Q
N
by inverting the HIGH input signal. When the bit line signal A input to the clear terminal CL becomes LOW, the flip-flop
60
is cleared and a HIGH signal D is output from the inverted output terminal Q
N
. Thus, by causing the flip-flop
60
to generate the signal D shown in
FIG. 5
, the timing of the charging completion of the bit line
32
is detected at the rising edge of the bit

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