Detection and recovery from connection failure in an ATM switch

Multiplex communications – Pathfinding or routing – Switching a message which includes an address header

Reexamination Certificate

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Reexamination Certificate

active

07075928

ABSTRACT:
An ATM switch according to the present invention includes a memory and a control circuit. The ATM switch generates a connection table in a memory, generates a multicast master entry including a limit field and a count field. The multicast master entry also includes address locations at which multicast ATM cells are stored. The ATM switch further generates one or more multicast member entries associated with said multicast master entry in said connection table, each multicast member entry identifying a destination connection on which said multicast ATM cells are to be transmitted. Further, the count field is initialized and the limit field is set at a predetermined value. The master entry is then determined to be active or inactive depending on a comparison between the count field and the limit field.

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IDT SWITCHStAR™ ATM Cell Based 1.24Gbps Non-Blocking Integrated Switch Controller Preliminary IDT77V500 Data Sheet.
IDT SWITCHStAR™ ATM Cell Based 8×8 1.24Gbps Non-Blocking Integrated Switching Memory Preliminary IDT77V400 Data Sheet.

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