Semiconductor device manufacturing: process – With measuring or testing
Reexamination Certificate
2000-06-29
2002-06-25
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
With measuring or testing
C438S015000, C438S018000
Reexamination Certificate
active
06410350
ABSTRACT:
TECHNICAL FIELD
The present invention relates to the field of semiconductor device fabrication processes, and more particularly to an apparatus and method for detecting speed variations across at die, a flash field, i.e. multiple dies, and multiple flash fields.
BACKGROUND INFORMATION
Semiconductor devices, such as integrated circuits, are typically formed on a section of a wafer of semiconductor material, such as silicon. The wafer includes multiple sections where each section is called a die. For example, a wafer having an eight-inch diameter may include up to 600 individual dies. Each die has an integrated circuit or chip disposed in the die.
The surface geometry of the various integrated-circuit components on a die is defined photographically. For example, the surface may be coated with a photosensitive layer and then exposed to light through a master pattern on a photographic plate, e.g., photo mask. The main body of the photo mask is a flat and transparent glass plate that defines the circuit pattern which may be 5× the size of the image to be transferred to the surface. The transfer of the image from the photo mask to the surface of the wafer is accomplished through the use of UV light and a photoresist. Photoresists are chemical compositions containing a light-sensitive material in suspension. Photoresists are coated on the wafer using a variety of techniques, e.g., contact printing, spinning.
One technique for exposing the photoresist is the “step and repeat” exposure. The equipment used for this technique is called a stepper. The stepper has a lens that photo reduces the image of a circuit pattern on the photo mask (reticle) onto a photosensitive substrate by a step and repeat scheme. A circuit pattern on a reticle is reduced and projected at a predetermined position (shot) onto a wafer surface through a projection optical system having a predetermined reduction ratio to be transferred. During the duration of the flash or exposure dose, multiple dies, i.e., “flash field”, may be flashed at one time. After the projection and transformation are performed once, the stage on which the wafer is placed is moved by a predetermined amount to transfer the image on another shot. These steps are repeated to entirely expose the wafer. The step and repeat process results in rows and columns of identical images. A similar technique uses a scanner to selectively expose layers of photoresist using slit-like exposure areas.
Unfortunately these techniques result in distortion or nonlinearity in the integrated circuits. These distortions may result in speed variations across the die. For example, the speed of the chip may be at different rates in different regions of the chip. If the speed in one region of the chip is unacceptable, then the chip is bad and marked for later identification. Hence, variations in the die speed affect yield and speed limitations. It is noted that variations in die speed may be caused by other factors occurring in any stage in the manufacturing process, e.g., oxidation, diffusion, deposition, patterning and etching.
One technique of attempting to quantify these variations implement scribe line monitors Scribe line monitors are placed in circuit-free street areas between the dies where the dies are detached, i. e, cut, removed, or scribed. Unfortunately, this technique only provides you with speed Variation information outside the die and not within tho die.
It would therefore be desirable to quantify these variations in die speed from data collected within the die and adjust the manufacturing process so as to improve the number of acceptable integrated circuits or chips disposed in the dies.
SUMMARY OF THE INVENTION
The problems outlined above may at least in part be solved in some embodiments by inserting a plurality of functional circuits at strategic locations across a die or a flash field, i.e., multiple dies, or multiple flash fields, where each of the plurality of functional circuits generate data, e.g., values, frequency, etc., that may be correlated to the die speeds at the strategic locations. Speed variations across the die, or flash field, or multiple flash fields may then be detected based on the data generated by the plurality of functional circuits. Upon analyzing the data generated by the plurality of functional circuits, the manufacturing process may then be adjusted, e.g., changing the exposure dose such as adjusting the exposure of a scanner or limiting the exposure field of a stepper.
In one embodiment, a method for detecting speed variations across a die comprises the step of determining at least one location of at least one critical region of the die. A critical region of the die is the location of a critical speed of the die. The method further comprises inserting a plurality of functional circuits at strategic locations across the die where each of the plurality of functional circuits generates data correlated to the die speeds at the strategic locations. The method further comprises reading the data of the plurality of functional circuits that is correlated to the die speeds at the strategic locations. Speed variations across the die are subsequently detected based on the data generated by the plurality of functional circuits.
In another embodiment of the present invention, a method for detecting speed variations across a flash field comprises the step of inserting a plurality of functional circuits at strategic locations across the flash field comprising multiple dies. Each of the plurality of functional circuits generates data correlated to the die speeds at the strategic locations. The method further comprises reading the data of the plurality of functional circuits that is correlated to the die speeds at the strategic locations. Speed variations across the flash field are subsequently detected based on the data generated by the plurality of functional circuits.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention.
REFERENCES:
patent: 4890270 (1989-12-01), Griffith
patent: 5457400 (1995-10-01), Ahmad et al.
patent: 5912562 (1999-06-01), Pappert et al.
patent: 5929650 (1999-07-01), Pappert et al.
patent: 6088830 (2000-07-01), Blomgren et al.
Dunn Michael James
Fenske Michael V.
Fuselier Mark Brandon
Ray Stephen Doug
Williams Roger T.
Advanced Micro Devices
Everhart Caridad
Voigt, Jr. Robert A.
Winstead Sechrest & Minick P.C.
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