Destuffing circuit with a digital phase-locked loop

Details Destuffing circuit with a digital phase-locked loop Destuffing circuit with a digital phase-locked loop

1986-12-29

1989-02-07

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

375120, H04J 307

Patent

active

048036803

ABSTRACT:
In a destuffing circuit for use in processing an input pulse sequence comprising data pulses, stuffing pulses, and control pulses into an output pulse sequence with reference to a data pulse timing signal, the output pulse sequence is produced with the stuffing and the control pulses removed from the input pulse sequence. A local signal producing arrangement produces a local signal by digital processing a predetermined one of first through M-th timing sequences derived from the data pulse timing signal and a preselected one of first through M-th local sequences derived from the local signal, where M represents a predetermined number. The destuffing circuit further comprises a destuffing arrangment responsive to the input sequence and produces the output pulse sequence by using the data pulse timing signal and the local signal.

REFERENCES:
patent: 3663760 (1972-05-01), De Witt
patent: 3781695 (1973-12-01), Jackson
patent: 4010323 (1977-03-01), Peck
patent: 4101739 (1978-07-01), Mueller
patent: 4143328 (1979-03-01), Kurita et al.
patent: 4280099 (1981-07-01), Rattlingourd
patent: 4397017 (1983-08-01), Rokugo
R. W. Furtney, Jr., "Digital Phase-Locked Loop", IBM Technical Disclosure Bulletin, vol. 17, No. 7, Dec. 1974, pp. 1884-1886.
J. S. Mayo, "Experimental 224 Mb/s PCM Terminals", The Bell System Technical Journal, vol. XLIV, No. 9 (Nov. 1965), pp. 1813-1841.
Hirokazu Goto, "A Digital Phase-Locked Loop for Synchronizing Digital Networks", International Conference Communication (San Francisco, California, Jun. 8-10, 1978), pp. 34-21 to 34-25.

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