Electricity: electrical systems and devices – Safety and protection of systems and devices – Load shunting by fault responsive means
Reexamination Certificate
2007-05-29
2007-05-29
Sircus, Brian (Department: 2836)
Electricity: electrical systems and devices
Safety and protection of systems and devices
Load shunting by fault responsive means
C361S111000
Reexamination Certificate
active
10365791
ABSTRACT:
A protection for ICs against ESD transients includes a circuit with a master circuit driving a slave circuit. The master circuit responds to ESD voltage V(t). The slave circuit comprises parallel shunt devices having common inputs. The output of the master circuit is coupled to the common inputs. As V(t) increases the master circuit applies a portion of V(t) to the input of the slave circuit shunt devices. The threshold voltage Vt1at which the slave circuit shunt devices would otherwise turn on to a lower value Vt1′ closer to the holding voltage Vh of the shunt devices. All of the slave circuit devices turn on substantially simultaneously at about Vt1′ close to Vh, thereby shunting the ESD transient to ground at a lower value of V(t). The master and slave circuits are inactive during normal IC operation.
REFERENCES:
patent: 5157573 (1992-10-01), Lee et al.
patent: 5255146 (1993-10-01), Miller
patent: 5477413 (1995-12-01), Watt
patent: 5978192 (1999-11-01), Young et al.
patent: 6100125 (2000-08-01), Hulfachor et al.
patent: 6249410 (2001-06-01), Ker et al.
patent: 6249413 (2001-06-01), Duvvury
patent: 6583972 (2003-06-01), Verhaege et al.
patent: 6775112 (2004-08-01), Smith et al.
patent: 7072161 (2006-07-01), Chen
patent: 2002/0033507 (2002-03-01), Verhaege et al.
patent: 0 851 552 (1998-01-01), None
patent: WO 01/97358 (2001-12-01), None
Chen, J.Z. et al., “Design Methodology and Optimization of Gate-Driven NMOS ESD Protection Circuits in Submicron CMOS Processes,”IEEE Transactions on Electron Devices, vol. 45, No. 12, p. 2448-2456 (Dec. 1998).
Polgreen, T.L. et al., “Improving the ESD Failure Threshold of Silicided n-MOS Output Transistors by Ensuring Uniform Current Flow,”IEEE Transactions on Electron Devices, vol. 39, No. 2, p. 379-388 (Feb. 1992).
Verhaege, et al., “Wafer Cost Reduction through Design of High Performance Fully Silicided ESD Devices”,EOS/ESD Symposium 00-18, 2000, pp. 18-28.
Duvvury, Charvaka, et al., “Dynamic Gate Coupling of NMOS for Efficient Output ESD Protection”,Proceedings of the IRPS, 1992, pp. 141-150.
May James T.
Tyler Larry E.
Barry Carol F.
Medtronic Inc.
Nguyen Danny
Sircus Brian
Soldner Michael C.
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