Deskewing clock signals for off-chip devices

Details Deskewing clock signals for off-chip devices Deskewing clock signals for off-chip devices

2000-01-13

2002-08-06

Cunningham, Terry D. (Department: 2816)

Miscellaneous active electrical nonlinear devices, circuits, and

Signal converting, shaping, or generating

Clock or pulse waveform generating

C327S565000, C327S158000

Reexamination Certificate

active

06429715

ABSTRACT:

TECHNICAL FIELD
This invention relates to deskewing of clock signals, and more particularly to deskewing of clock signals for off-chip devices.
BACKGROUND INFORMATION
FIG. 1
(Prior Art) is a simplified top-down diagram of a field programmable gate array (FPGA) integrated circuit
1
. Integrated circuit
1
includes a ring of interface cells
2
(sometimes called “I/O cells”) and an inner core of configurable logic blocks (not shown). Each configurable logic block (CLB) contains one or more sequential logic elements. These sequential logic elements are represented in
FIG. 1
as flip-flops
3
. A clock signal that is received from an off-chip source is typically routed via a clock bus to numerous clock inputs of the flip-flops so that all the flip-flops are clocked together. To prevent a given clock edge from being received at one of the flip-flops before it is received at another (this is called “clock skew”), a structure called a “balanced clock tree” is employed.
FIG. 2
(Prior Art) is a simplified diagram illustrating a balanced clock tree
4
. The distance a clock signal must travel from the clock source at point CS to any of the points A-H at the respective clock inputs of flip-flops
5
-
12
is identical. Assuming equal propagation speeds through the various branches of this balanced clock tree, the clock signal at point CS will reach points A-H at the same time. In the structure of
FIG. 2
there will, however, be a propagation delay between the time a given clock edge arrives at point CS and the time when that clock edge arrives at points A-H. Where a clock signal edge is received onto an FPGA from an external source, such a propagation delay may introduce undesirable clock skew between the clock signal edge where it enters the FPGA and the clock signal edge at the clock inputs of the various flip-flops inside the integrated circuit. A circuit called a “delay-locked loop” (DLL) may be employed to reduce such clock skew.
FIG. 3
Prior Art) is a simplified diagram of FPGA
1
that uses a “delay-locked loop” (DLL)
13
to eliminate such clock skew. An external clock signal CLKIN is received onto FPGA
1
via a clock input buffer
14
and is supplied to a reference signal input
15
of DLL
13
. DLL
13
has a feedback signal input
16
which is coupled to the clock input of flip-flop
5
by a short connection
17
. DLL
13
delays the clock signal output by the DLL on DLL output
18
such that the phase of the clock signal at clock feedback input
16
matches the phase of the clock signal at clock input
15
. The connection
17
from the clock input of flip-flop
5
to the feedback signal input
16
is made to have the same delay as the delay through clock input buffer
14
to reference signal input
15
. Accordingly, the phase of the clock signal at the clock inputs of flip-flops
5
-
12
matches the phase of the clock signal where CLKIN is received onto FPGA
1
at the input of clock input buffer
14
. The clock signal at the clock inputs of flip-flops
5
-
12
is therefore said to be “deskewed” with respect to the external clock signal CLKIN. For additional background information on DLLs and/or their uses in FPGAs, see: 1) U.S. patent application Ser. No. 09/102,740, entitled “Delay Lock Loop With Clock Phase Shifter”, filed Jun. 22, 1998, by Hassoun et al.; 2) U.S. patent application Ser. No. 09/363,941, entitled “Programmable Logic Device With Delay-Locked Loop”, filed Jul. 29, 1999, by Schultz et al.; and 3) U.S. Pat. No. 5,646,564 (the content of these three documents is incorporated herein by reference).
An FPGA may be used to drive another integrated circuit in a synchronous fashion.
FIG. 4
(Prior Art) is a diagram of an implementation wherein FPGA
1
is configured to realize RAM control circuitry
20
for interfacing with an external Random Access Memory (RAM) integrated circuit
21
.
FIG. 5
(Prior Art) is a waveform diagram representative of signals associated with the reading of information from RAM
21
.
RAM control circuitry
20
is synchronous logic realized using flip-flops inside FPGA
1
. The internal clock signal that clocks these flip-flops is deskewed with respect to the external clock signal CLKIN using DLL
13
as described above in connection with FIG.
3
. RAM control circuitry
20
also supplies the clock signal CLK to external RAM
21
via an interface cell
23
and an external clock line
24
. To read data from a given memory location, RAM control circuitry
20
outputs the address ADDR of the memory location to be read via interface cells
25
and external address bus lines
26
. (The single interface cell
25
RAM in
FIG. 4
represents a plurality of interface cells that drives the address bus lines
26
.) RAM control circuitry
20
also outputs a control signal CONTROL via interface cell
27
and line
28
. Control signal CONTROL indicates that the operation is a read operation as opposed to a write operation.
RAM
21
examines the address ADDR and the control signal CONTROL on a rising edge
29
of the clock signal CLK. If the operation is a read operation, RAM
21
supplies the requested data back to the FBGA
1
via data bus lines
30
. The RAM
21
therefore requires that the control signal CONTROL be valid at RAM
21
a given setup time before the rising edge
29
of the clock signal and remain stable a given hold time after the rising edge
29
.
Because RAM control circuitry
20
is synchronous logic, clock edge
31
triggers the output of the control signal CONTROL. There is delay associated with producing and conducting this control signal to RAM
21
. That delay results in control signal CONTROL arriving at RAM
21
a given time later at time
32
. Similarly, clock edge
33
causes the RAM control circuitry
20
to remove the control signal CONTROL. It is removed a given time after clock edge
33
at time
34
. As seen in
FIG. 5
, increasing the propagation delay of the clock signal between FPGA
1
and RAM
21
serves to delay the clock signal CLK AT RAM. Delaying the clock signal CLK AT RAM results in a decreased hold time
35
. If this hold time
35
is too short, then the hold time required by the RAM
21
will be violated.
FIG. 6
(Prior Art) is a diagram of one conventional solution wherein a second DLL
36
deskews the clock signal CLK at point
38
on RAM
21
. The connection from point
37
to point
38
and the connection from point
37
to point
39
are fashioned to have the same propagation delays. DLL
36
therefore delays the clock signal CLK such that the phase of the clock signal CLK at point
38
matches the phase of the clock signal at point
39
. Because the propagation delays through the two input buffers leading into DLL
36
are the same, the phase of the clock signal CLK at point
38
matches the phase of the external clock signal CLKIN where it enters FPGA
1
at point
40
.
The bottom waveform CLK AT RAM (WITH DLL) in
FIG. 5
illustrates the clock signal CLK at point
38
. Note that the phase of this clock signal CLK AT RAM in the bottom waveform matches the phase of the external clock signal CLKIN in the top waveform. Because the clock skew between clock signals at points
40
and
38
is eliminated, the hold time
41
between the rising edge
42
of the clock signal at RAM
21
and the control signal CONTROL is increased.
It may also be desired that such an FPGA interface with more than one external device in synchronous fashion.
FIG. 7
(Prior Art) is a diagram of one conventional technique. The second DLL
36
deskews the clock signal CLK at the various external devices
56
-
59
with respect to the external clock signal CLKIN at point
40
as in the example of FIG.
6
. The circuit of
FIG. 7
, however, employs a balanced clock tree so that the clock signal CLK from point
37
reaches the clock inputs
44
-
47
of all the RAM chips
56
-
59
at the same time. As in the example of
FIG. 6
, the propagation delay from point
37
to point
44
is made to match the propagation delay from point
37
to point
39
. Because the delays through the two clock input buffers leading into DLL
36
are th

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