Designing of a logic circuit for testability

Details Designing of a logic circuit for testability Designing of a logic circuit for testability

2002-07-05

2008-10-14

Hirl, Joseph P (Department: 2129)

Data processing: artificial intelligence

Knowledge processing system

Knowledge representation and reasoning technique

C706S046000, C706S045000

Reexamination Certificate

active

07437340

ABSTRACT:
The area of the circuit to be added for easy testability is reduced. Operations contained in a behavioral description are extracted in an operation analyzing unit; when expanding any operation at the time of behavioral synthesis, if the area of the circuit can be reduced to a greater extent when a DFT is applied to the operation before expansion, a parameter indicating that the operation is not to be expanded at the time of behavioral synthesis is generated and DFT information is added to a DFT library. A behavioral synthesis unit, in accordance with the parameter, generates an RTL description without expanding the operation. A DFT unit implements the DFT by referring to the DFT library, and thereafter expands the operation.

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Takabatake, et al., “Non-Scan Design for Testable Data Paths Using Thru Operation”, IEEE, Mar. 1997, pp. 313-318.
Ohtake, et al., “A Non-Scan DFT Method for Controllers to Achieve Complete Fault Efficiency”, IEEE, Sep. 1998, pp. 204-211.
Wada, et al., “A Non-Scan DFT Method for Data Paths to Provide Complete Fault Efficiency” IEICE Transaction D-I, vol. J82-D-I, No. 7, pp. 843-851, Jul. 1999. (See p. 1, lines 11-18 of the specification for brief explanation).

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