Design tools for high-level synthesis of a low-power data path

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364491, G06F 1750

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active

058318640

ABSTRACT:
A computer-aided design tool and associated methods address the problem of high-level behavioral synthesis, useful in the design of semiconductor integrated circuit for minimum power consumption. The tool makes a plurality of types of power reducing changes, and evaluates the results using iterative improvement. In a particular embodiment, "moves" corresponding to alterations of scheduling of operations or resource sharing are iteratively proposed and evaluated with a power "cost function" defined by summing estimates of the switched capacitance of each resource element. In an extension of that embodiment, moves corresponding to alterations of module selection and clock selection are also evaluated.

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