Boots – shoes – and leggings
Patent
1996-10-01
1999-07-27
Teska, Kevin J.
Boots, shoes, and leggings
364489, 364490, 364491, 364578, G06F 1700, G06F 1750
Patent
active
059301473
ABSTRACT:
A design support device 1 has a module division and merger section 8 for receiving a result from a HDL analysis section 6 to analyze a HDL description of a RTL and for dividing and merging the modules based on instructions from outside or automatically, a module allocation section 10 for allocating the modules by using the result from the module division and merger section 8 and the analyzed result by the HDL analysis section 6, a budgeting section 11 for budgeting an area, a shape, a timing, and a power consumption to each of the modules allocated by the module allocation means 10, and an estimation section for estimating module information for the result from the module division and merger section 8 and the result from the module allocation section 10.
REFERENCES:
patent: 5491640 (1996-02-01), Mahmood et al.
patent: 5519627 (1996-05-01), Mahmood et al.
patent: 5541850 (1996-07-01), Vander Zanden et al.
patent: 5544071 (1996-08-01), Keren et al.
patent: 5623418 (1997-04-01), Rostoker et al.
patent: 5726902 (1998-03-01), Mahmood et al.
patent: 5764525 (1998-06-01), Mahmood et al.
Ramachandran et al "Combined Topological and Functionality-Based Delay Estimation Using a Layout-Driven Approach for High-Level Applications,"IEEE, pp. 1450-1460, Dec. 1994.
Kedem et al "ASIC Design with OASIS," IEEE, pp. 2580-2583, 1990.
Kumar et al "Emulation Verification of the Motorola 68060", IEEE, pp. 150-158, Oct. 1995.
Fischer et al "NETHDL: Abstract of Schematics to High-Level HDL," IEEE, pp. 90-96, Mar. 1990.
Hu et al "A Methodology for Design Verification," IEEE, pp. 236-239, Sep. 1994.
Paulin et al "High-Level Synthesis and Codesign Methods: An Application to a Verification Codec," IEEE, pp. 444-451, Sep. 1995.
Kabushiki Kaisha Toshiba
Siek Vuthe
Teska Kevin J.
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