Design rules checker for an integrated circuit design

Details Design rules checker for an integrated circuit design Design rules checker for an integrated circuit design

1997-06-30

1999-11-16

Stamber, Eric W.

G06F 1750

Patent

active

059872403

ABSTRACT:
A design rule checker for verifying that an integrated circuit design meets one or more geometrical constraints, the integrated circuit design being expressed as a graph data structure having at least a root node connected by a plurality of paths to one or more leaf nodes so that a single leaf node can represent multiple instances of a geometrical shape. In the preferred embodiment, the design rule checker includes: means for generating a flattened graph data structure in which each instance of the primitive geometrical shape is separately represented; means for scanning the flattened data structure to generate an error report comprising a plurality of error records representing violations of a geometrical constraint by a geometrical shape, wherein each error record includes a sortable index representing the path in the graph data structure from a root node to the geometrical shape giving rise to an error; and means for sorting the error report and for identifying the error records according to the sortable indices representing the paths through the graph data structure.

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