Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
1999-12-09
2003-06-10
Broda, Samuel (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S016000, C716S030000, C382S280000
Reexamination Certificate
active
06577994
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a design rule generation and, in particular, a system for automatically generating a design rule and a recording medium recording a program thereof.
2. Description of the Background Art
In recent years, to comply with the high integration and miniaturization of semiconductor integrated circuits, there proceeds rapidly the miniaturization of resist patterns formed on wafers and that of mask patterns for forming the resist patterns. In photolithography technique, super resolution technique is used as one method other than shortening the wavelength of light source, for improving resolution such as to comply with the miniaturization. Examples of the super resolution technique are so-called Levenson method and modified illumination method.
In the Levenson method, by disposing a phase shifter on a mask, the resolution of a resist pattern formed on a wafer is increased to comply with the miniaturization. In the modified illumination method, by changing the shape of a light source itself, the resolution of a pattern formed on a wafer is increased to comply with the miniaturization. With these super resolution techniques, a further fine resist pattern can be formed, but there is the possibility of causing a different dimensional change than has hitherto been caused.
Specifically, in a method employing no super resolution technique, any layouts in which line width and space width are below resolution limit are prohibited, and a mask pattern is laid out such that line width and space width are not less than the resolution limit. Thereby, no large dimensional change occurs between the mask pattern and the pattern formed on a resist (finished pattern), and the dimensional change in the finished pattern falls within a predictable range. When employing a super resolution technique, line width and space width that are resolution limits can be reduced. In a certain dimensional range, however, the finished pattern size is far thick or thinner than a mask pattern, resulting in beyond a permitted limit in some cases. Further, it may on occasion be difficult to predict this. As a technique for solving this problem, optical simulation has been used in recent years.
Optical simulation is a technique for predicting the shape of a finished pattern. This enables to make a design rule (referred to simply as a “DR” in some instances) corresponding to a super resolution technique, based on the predicted shape of the finished pattern.
Now, a schematic flow chart of a semiconductor device manufacture is given in FIG.
23
. In the manufacture of a semiconductor device, as shown in
FIG. 23
, a circuit design and its verification are performed (step S
101
) and, based on the designed circuit data, a layout design and its verification for determining an actual circuit pattern formed on a wafer are performed (step S
102
). Then, based on the layout design, a wafer process is executed (step S
103
). The design rule is used for the layout design and verification shown in step S
102
. That is, it is the rule for specifying, for example, the line width of wiring and the space width of wirings, and is restricted by wafer process.
In photolithography being one wafer process, when no super resolution technique is employed, a design rule of the same layer is relatively simple. Specifically, all required therefor is to specify a minimum line width (L) and minimum space width (S) which show the wafer process limit (e.g., a resolution limit in photolithography).
On the other hand, when a super resolution technique is employed in a wafer process, a complicated design rule is required to comply with the super resolution technique. For example, in forming a wiring pattern having various space widths S, as shown in
FIG. 24
, it is insufficient only by specifying a minimum line width L and minimum space width S, and thus required to determine whether resolution is executable or not in a combination of a line width and space width, namely, whether the finished pattern size exceeds a permitted limit or not.
Then, for satisfying this requirement, a method of making a matrix table as shown in
FIG. 25
, has been taken.
FIG. 25
shows a so-called L/S matrix that is a table in which various numerical values of line width and space width of a wiring pattern are disposed vertically and laterally, respectively, in order to make understandable a plurality of combinations of line width and space width.
Referring to
FIG. 25
, disposed vertically are the numerical values of line width L (unit: &mgr;m). These are disposed at intervals of 0.02 &mgr;m in the range from 0.14 &mgr;m to 0.4 &mgr;m, at intervals of 0.1 &mgr;m in the range from 0.4 &mgr;m to 1.2 &mgr;m, and the last numerical value is 1.5 &mgr;m or more. Disposed laterally are the numerical values of space width S. These are disposed at intervals of 0.02 &mgr;m in the range from 0.14 &mgr;m to 0.4 &mgr;m, at intervals of 0.1 &mgr;m in the range from 0.4 &mgr;m to 1.2 &mgr;m, and the last numerical value is 1.5 &mgr;m or more. In this table, for instance, region A covers the line width L of 0.30 &mgr;m to 0.32 &mgr;m, and the space width of 0.24 &mgr;m to 0.26 &mgr;m.
Referring now to
FIGS. 26 and 27
, a method of using a L/S matrix is described.
FIGS. 26 and 27
express the L/S matrix of
FIG. 25
, for general purpose. Although no specific values of line width L and space width S are indicated, it is set such that line width L increases as it moves downward in the vertical direction, and space width S increases as it moves rightward in the lateral direction.
FIG. 26
is a table illustrating the resolvability based on the calculation result obtained by optical simulation, when no super resolution technique is employed. Region A
1
of the hatched part corresponds to the region covering combinations of line width and space width, with which an optical image of a pattern defined by lines and spaces is resolvable on an image surface of an optical system in photolithography, e.g., on a resist.
The region A
1
is of a simple rectangle. Thus, it will be apparent that the region A
1
can be specified as a design rule, merely by specifying the minimum line width and minimum space width which show a resolution limit in photolithography.
On the other hand,
FIG. 27
is a table illustrating the resolvability based on the calculation result obtained by optical simulation, when the modified illumination method is employed as a super resolution technique. Regions A
1
and A
2
of the hatched part correspond to the region covering combinations of line width and space width, with which an optical image of a pattern defined by lines and spaces is resolvable on a resist. The region A
2
is such a region that surrounds the corner of the region A
1
, and is a peculiar result when used an aperture for annular illumination in the modified illumination method. It will be apparent that the shape of the resolvable region is complicated by the presence of the region A
2
, thus requiring a complicated rule for specifying that region as a design rule.
As described in the foregoing, when the super resolution technique is employed in a wafer process in order to comply with the high integration and miniaturization of semiconductor integrated circuits, a complicated design rule is required for complying with the super resolution technique. Hitherto, the design rule has been obtained by the following manner. That is, the designer sequentially makes an optical simulation to various combinations of line width L and space width S, to make a L/S matrix, and determines whether resolution is executable or not, in the respective combinations of line width and space width, by using the L/S matrix. Based on the results, a design rule is determined empirically. Thus, the efficiency of operation to determine a design rule is poor, and a long time is required to determine the design rule. Further, it is impossible to make determination for all the combinations, and thus limited to checking of every important point.
SUMMARY OF THE INVEN
Broda Samuel
Mitsubishi Denki & Kabushiki Kaisha
Phan Thai
LandOfFree
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