Design rule checking using serial neighborhood processors

Details Design rule checking using serial neighborhood processors Design rule checking using serial neighborhood processors

1982-01-19

1984-04-03

Boudreau, Leo H.

Image analysis

Histogram processing

For setting a threshold

364490, 364560, 382 25, 382 27, 382 41, 382 49, G06K 936

Patent

active

044412070

ABSTRACT:
A pipeline of programmable serial neighborhood stages is used to automatically check for adherence to a set of predetermined geometrical constraints or design rules used in the fabrication of electronic components such as integrated circuit devices. In a disclosed embodiment, bit-map representations of several IC masks are superimposed in one composite image matrix for processing in the pipeline. Advantages in processing speed, especially for design rule checking requiring data from more than one mask, are obtained since all necessary data is available to the stages in the pipeline.

REFERENCES:
patent: 4167728 (1979-09-01), Sternberg
patent: 4242662 (1980-12-01), Tsujiyama et al.
patent: 4300122 (1981-11-01), McMahon
patent: 4301443 (1981-11-01), Sternberg et al.
patent: 4345312 (1982-08-01), Yasuye et al.
Baker et al., "Tools for Verifying Integrated Circuit Designs," Lamda, Fourth Quarter, 1980.
Baker, "Artwork Analysis Tools for ULSI Circuits," (M.S. Thesis) MIT, 1980.
Seiler, "Special Purpose Hardware for Design Rule Checking," Private Communication, in Preparation for Second Caltech Conference on Very Large Scale Integration, Jan. 10-21, 1981.
Baird, "Fast Algorithms for LSI Artwork Analysis," Journal of Design Automation and Fault Tolerant Computing, vol. 2, No. 2, May 1978.

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