1997-09-18
2000-06-20
Teska, Kevin J.
39550006, G06F 1750
Patent
active
060787376
ABSTRACT:
A design rule check is to inspect whether mask pattern data of a semiconductor integrated circuit is correctly designed in accordance with a design standard or not. A design rule check method of the present invention is characterized in that design rule check errors occurring in the design rule check between a first error and a second error output in accordance with whether the design rule check errors overlap or not.
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Bhat et al., "Special Purpose Architecture for Accelerating Bitmap DRC" 26th ACM/EEE Design Automation Conference pp. 674-677 (Jan. 1989).
Crawford et al., "Computer verification fo Large Scale Integrated Circuit Masks" IEEE pp. 132-135 (1978).
Modarres et al., "A Formal Approach to Desing-Rule Checking" IEEE Transactions on Computer-Aided Design pp. 561-573 (1987), vol. CAD-6, No. 4, Jul. 1987.
Hedenstierna et al. ("The halo algorithm--an algorithm for hierarchical design of rule checking of VLSI circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 12, No. 2, Feb. 1993, pp. 265-272.
Kik Phallaka
NEC Corporation
Teska Kevin J.
LandOfFree
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