Design of device layout for integration with power mosfet packag

Details Design of device layout for integration with power mosfet packag Design of device layout for integration with power mosfet packag

1996-09-10

1998-06-16

Saadat, Mahshid D.

Active solid-state devices (e.g., transistors, solid-state diode

Lead frame

257401, H01L 23495

Patent

active

057675678

ABSTRACT:
The present invention discloses a MOSFET power IC device formed in a semiconductor chip including a source contact area which is provided for connecting to a lead-frame via a several of lead-wires. The power IC device includes many lead-wire contact points on the source contact area for securely attaching the lead wires onto the source contact area. These lead-wire contact points are uniformly distributed substantially over the source contact area thus the spread resistance is reduced whereby the device on-resistance and device performance may be improved.

REFERENCES:
patent: 5306937 (1994-04-01), Nishimura
patent: 5497013 (1996-03-01), Temple
patent: 5544038 (1996-08-01), Fisher et al.
patent: 5661315 (1997-08-01), Bauer et al.

Affiliated with

Also associated with

Rating

Design of device layout for integration with power mosfet packag does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Design of device layout for integration with power mosfet packag, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design of device layout for integration with power mosfet packag will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1729223