Data processing: structural design – modeling – simulation – and em – Structural design
Reexamination Certificate
1999-01-21
2001-08-14
Teska, Kevin J. (Department: 2123)
Data processing: structural design, modeling, simulation, and em
Structural design
C703S019000, C716S131000
Reexamination Certificate
active
06275784
ABSTRACT:
FIELD OF THE INVENTION
This invention relates to a design method for a semiconductor integrated circuit device and, more particularly, to a design method for routing signal lines between circuit blocks on a semiconductor chip and a semiconductor integrated circuit device designed therethrough.
DESCRIPTION OF THE RELATED ART
Various circuit blocks are incorporated in a semiconductor integrated circuit device, and the function of some circuit blocks is identical. The circuit blocks with an identical function are hereinbelow referred to as “identical blocks”. It is important for the manufacturer to eliminate differences in electric characteristics such as timing from the identical blocks, because a time lag results in a malfunction of the semiconductor integrated circuit device. A capacitive coupling between the parallel signal lines and a capacitive coupling between the crossing signal lines strongly affect the signal propagation speed designed under sever design rules. Especially, the circuit blocks affect signals on the signal lines adjacent thereto.
A design method for eliminating the undesirable influence from the circuit blocks is disclosed in Japanese Patent Publication of Unexamined Application No. 5-343523. The prior art design method partially or completely prohibits a designer from passing signal lines through a zone over identical blocks.
FIG. 1
illustrates the prior art design method.
The prior art design work starts with extraction of identical blocks from pieces of design information representative of circuit blocks to be integrated on a semiconductor chip and interconnections therebetween as by step SPI. A piece of design information is representative of prohibition rules where a designer is not allowed to pass signal lines, and is added to the identical blocks. Then, the circuit designer is prohibited from passing signal lines over the identical blocks as by step SP
2
.
Subsequently, the circuit blocks are arranged on the semiconductor chip as by step SP
3
. The area occupied by each circuit block and the interconnections are taken into account for the arrangement of the circuit blocks. A circuit block is selected from those circuit blocks on the semiconductor chip, and is connected to another circuit block through a signal line or lines as by step SP
4
. After step SP
4
, the pieces of design information are checked to see whether or not all the signal lines have been connected between circuit blocks as by step SP
5
.
If the answer at step SP
5
is given negative, the control returns to step SP
4
, and reiterates the loop consisting of steps SP
4
and SP
5
until change from negative to affirmative. While the control is reiterating the loop, pairs of nodes a
1
/a
2
, b
1
/b
2
, c
1
/c
2
, d
1
/d
2
and e
1
/e
2
to be connected are on both sides of the identical blocks
1
/
2
as shown in FIG.
2
. The identical blocks
1
and
2
are arranged in symmetry with respect to a routing lattice
3
as indicated by capital letter “F”. However, signal lines are prohibited from passing through the zones over the identical blocks
1
/
2
. The prohibited zones are indicated by hatching lines. For this reason, the designer has to route signal lines
4
a
/
4
b
/
4
c
/
4
d
/
4
e
outside the peripheries of the identical blocks
1
/
2
, and the signal lines
4
a
/
4
b
/
4
c
/
4
d
bypass the prohibited zones. When all the signal lines are connected between the circuit blocks, the answer at step SP
5
is given affirmative, and the design work is completed.
Another prior art design method renders signal lines to pass an area between pairs of identical circuits arranged in symmetry.
FIG. 3
illustrates the layout of an integrated circuit fabricated on a semiconductor chip. Reference numerals
5
a
/
5
b
,
6
a
/
6
b
and
7
a
/
7
b
designate pairs of identical blocks. The identical blocks
5
a
/
6
a
/
7
a
are arranged in symmetry with the identical blocks
5
b
/
6
b
/
7
b
as indicated by capital letter “F”. The area between the identical blocks
5
a
/
6
a
/
7
a
and
5
b
/
6
b
/
7
b
is assigned to a virtual lattice available for signal lines, and the line of symmetry extends through the area. If nodes a
1
/a
2
are to be connected, a signal line
8
extends through the area between the identical blocks
5
a
/
6
a
/
7
a
and the identical blocks
5
b
/
6
b
/
7
b.
However, the semiconductor integrated circuit devices have become complicated, the designers encounter the following problems in the prior art design methods. When the manufacturer designs the complicated integrated circuit device through the first prior art design method, the first design method requires a large semiconductor chip. In detail, a large number of identical blocks are incorporated in the complicated integrated circuit device, and the first prior art design method prohibits the designer from using the zone over each identical block. The identical blocks occupy wide area, and the prohibited zone is so much. The signal lines have to bypass the prohibited zone, and require additional area around the identical blocks. The additional area enlarges the semiconductor chip. Assuming now that one of ten signal lines has nodes to be connected over an identical block equivalent to 200 lines of the routing lattice, the designer has to route 20 signal lines around the identical block, and the 20 signal lines requires the additional area at least 10 percent of the area occupied by the identical block.
On the other hand, the manufacturer encounters a problem in the second prior art design method in many limitations on the routing work. In detail, the second prior art design method requires a line of symmetry passing between identical blocks paired with each other. If the line of symmetry is not found, the designer can not route a signal line beside an identical block. For example, if the identical block
5
a
is located in an area on the right side of the identical block
5
b
, the pair of identical blocks
5
b
/
5
a
interrupts the line of symmetry, and the designer can not connect the nodes a
1
/a
2
through the signal line
8
. If the designer connects the nodes a
1
/a
2
through the signal line
8
, the signal line affects the identical block
5
b
only, and the identical blocks
5
a
/
5
b
can not equivalently behave in the integrated circuit device. For this reason, the designer needs to rearrange the circuit blocks on the semiconductor chip.
SUMMARY OF THE INVENTION
It is therefore an important object of the present invention to provide a design method for routing signal lines which allows a designer to connect nodes on both sides of identical blocks without additional area and a line of symmetry.
It is also an important object of the present invention to provide a semiconductor integrated circuit device, which has identical blocks identical in circuit characteristics with one another.
To accomplish the object, the present invention proposes to branch a conductive line from another conductive line so that the branched signal lines extend over all the certain circuit blocks.
In accordance with one aspect of the present invention, there is provided a design method for routing conductive lines between nodes to be electrically connected comprising the steps of selecting certain circuit blocks expected to be identical in circuit characteristics with one another from circuit blocks to be integrated on a substrate, arranging the circuit blocks in an area of the substrate and routing conductive lines between the circuit blocks, wherein, if one of the conductive lines passes over one of the certain circuit blocks, at least one conductive sub-line is branched from the aforesaid one of the conductive lines in order to pass another of the certain circuit blocks.
In accordance with another aspect of the present invention, there is provided a semiconductor integrated circuit device fabricated on a semiconductor chip comprising a plurality of circuit blocks having certain circuit blocks to be identical in circuit characteristics with one another and a plurality of conductive lines selectively connected between the plurality
McGinn & Gibb PLLC
NEC Corporation
Phan Thai
Teska Kevin J.
LandOfFree
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