Design for testability technique of CMOS and BICMOS ICS

Details Design for testability technique of CMOS and BICMOS ICS Design for testability technique of CMOS and BICMOS ICS

1995-01-24

1996-12-03

Canney, Vincent P.

Excavating

371 225, G06F 1100

Patent

active

055815634

ABSTRACT:
A DFT technique for the detection of bridging faults in CMOS and BiCMOS logic ICs, employs purposely integrated monitoring inverters, driven by signal nodes of the functional circuits to be tested, for revealing the presence of intermediate voltages of a critical value. The monitoring inverters are supplied through a dedicated shadow line that is connected to either one of the supply rails of the functional circuits through a load: a resistance, for a static implementation, or a capacitor, for a dynamic (clocked) implementation. Absence of series connected built-in current sensors (BICSs) avoids degradation of the performance of the functional circuits and is compatible with scaling down of the power supply and with on-line testing techniques. Only critical bridging faults may be reliably and selectively detected, thus reducing the number of rejects, failing a conventional IDDQ test. In a modified embodiment, a DFT scheme of the invention may be adapted to reveal also stuck-at faults, by connecting together the output nodes of certain monitoring inverters to create activatable current paths from a test node (shadow line) and a supply rail of the IC.

REFERENCES:
patent: 5025344 (1991-06-01), Maly et al.
patent: 5390193 (1995-02-01), Millman et al.
"Random Current Testing for CMOS Logic Circuits by Monitoring a Dynamic Power Supply Current" by Tamamoto et al, Dept. of Information Engineering, Mining College, Akira University Sep. 7, 1992.
"Design of ICs Applying Built-In Current Testing" by Maly et al., Journal of Electronic Testing: Theory And Applications Dec. 1992.

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