Design for testability technique for phase detectors used in...

Details Design for testability technique for phase detectors used in... Design for testability technique for phase detectors used in...

2007-11-30

2009-12-08

Dunn, Drew A (Department: 2863)

Data processing: measuring, calibrating, or testing

Measurement system in a specific environment

Electrical signal parameter measurement system

Reexamination Certificate

active

07630846

ABSTRACT:
A method and circuit for testing phase detectors in a delay locked loop is provided. The method includes storing output from a first phase detector and from a second phase detector when the counter is at the +0, +1, and −1 counter positions, and comparing the results to determine whether a phase detector is faulty. The circuit implementing this technique uses a second phase detector configured to receive the signals entering a first phase detector. Particularly, the circuit is routed such that a signal entering the D input of the first phase detector is inputted into the clock input of the second phase detector, and a signal entering the clock input of the first phase detector is inputted into the D input of the second phase detector. The circuit is also coupled to a test controller located on-die or at a high volume manufacturing (HVM) tester.

REFERENCES:
patent: 4890056 (1989-12-01), Peters et al.
patent: 2008/0172193 (2008-07-01), Rhee et al.

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