Design-for-testability method for path delay faults and test pat

Details Design-for-testability method for path delay faults and test pat Design-for-testability method for path delay faults and test pat

1996-08-26

1998-05-05

Nguyen, Hoa T.

Excavating

G01R 3128

Patent

active

057486468

ABSTRACT:
There is provided a design-for-testability method for path delay faults capable of assuring high fault coverage without any substantial increase in area overhead. In a given integrated circuit, an initial pattern is generated for the path delay fault selected, and logical values set for scan flip-flops in the initial pattern are stored. A transition pattern is generated for the selected path delay fault. It is judged whether or not the integrated circuit contains a scan flip-flop of which logical value set in the initial pattern is contradictory to the logical value set in the transition pattern. In the affirmative, a value holding element, for example a D latch, having a function of once holding an input data, is inserted in the output signal line of the scan flip-flop presenting a contradiction in logical value. This D latch eliminates a contradiction in logical value in the initial and transition patterns, thereby to prevent the generation of a test pattern from meeting with failure. This results in improvements in path delay fault coverage.

REFERENCES:
patent: 5625630 (1997-04-01), Abramovici
I. Pomeranz et al., "Design-for Testability for Path Delay Faults in Large Combinational Circuits Using Test-Points", proc. of 31st ACM/IEEE Design Automation conference, 1994, pp. 358-364.
K. Cheng et al., "Generation of High Quality Non-Robust Tests for Path Delay Faults", proc. of 31st ACM/IEEE Design Automation Conference, 1994, pp. 365-369.

Affiliated with

Also associated with

Rating

Design-for-testability method for path delay faults and test pat does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Design-for-testability method for path delay faults and test pat, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Design-for-testability method for path delay faults and test pat will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-63380