Design-for-test modes for a phase locked loop

Details Design-for-test modes for a phase locked loop Design-for-test modes for a phase locked loop

2005-02-22

2005-02-22

Nguyen, Vincent Q. (Department: 2858)

Electricity: measuring and testing

Measuring, testing, or sensing electricity, per se

Frequency of cyclic current or voltage

C327S156000, C327S157000, C331S025000

Reexamination Certificate

active

06859028

ABSTRACT:
There is a desire to provide a testing method and apparatus that can be successfully integrated into a PLL and PLL-like circuits (e.g. frequency synthesizers, delay lock loops, etc.). It is desirable that the PLL or PLL-like circuit integrated with testing apparatus does not suffer from performance degradations during nominal (mission mode) operation. Furthermore, it is desirable that the PLL and the testing apparatus share the same interface. In order to produce a PLL having integrated testing apparatus, without having the PLL suffer severe performance degradations during nominal operation nor having the combination of the PLL and testing apparatus be unnecessarily large, a modified PLL integrated with testing apparatus is provided.

REFERENCES:
patent: 5903748 (1999-05-01), McCollough et al.
patent: 5933058 (1999-08-01), Pinto et al.
patent: 5991888 (1999-11-01), Faulkner et al.

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