Design-for-test circuit for successive approximation...

Details Design-for-test circuit for successive approximation... Design-for-test circuit for successive approximation...

2000-08-18

2003-05-20

Jeanpierre, Peguy (Department: 2819)

Coded data generation or conversion

Converter calibration or testing

C341S163000

Reexamination Certificate

active

06567021

ABSTRACT:

FIELD OF THE INVENTION
This invention relates generally to the field of electronic design and test, and specifically to the field of mixed-signal IC design for test (DfT).
BACKGROUND OF THE INVENTION
Two important performance measurements for analog to digital converters (ADCs) are integral non-linearity (INL) and differential non-linearity (DNL). These test are very time consuming, and lead to very high production testing costs. In prior art test methodologies, successive approximation analog-to-digital converters (ADCs) have been tested using a histogram approach to measure integral nonlinearity (INL) and differential nonlinearity (DNL). The input to the ADC can be either a voltage ramp, voltage triangle (up ramp/down ramp) or a sine wave. Both the ramp and sine wave histogram techniques are documented in Chapters 11 and 12 of the book “An Introduction to Mixed-Signal IC Test and Measurement” by Mark Burns. The objective of either test approach is to measure the range of input voltages that produce each of the possible digital outputs from the ADC. The voltage levels that correspond to the transitions from one code to the next are called decision levels. The voltage ranges corresponding to each ADC code are referred to as step sizes.
If the step sizes for each code are not substantially equal to one another, the converter is said to be non-linear. Integral nonlinearity is the measurement of the maximum positive deviation and maximum negative deviation of the actual decision levels from the ideal decision levels. Differential nonlinearity is the measurement of the difference between one step size and the next, relative to the average step size across all ADC codes. Measurement of INL and DNL therefore requires that one knows the ADC input voltage corresponding to each decision level.
The measurement of ADC INL and DNL is very time consuming, driving up the cost of production testing of mixed-signal devices containing ADCs. Every additional bit of ADC converter resolution doubles the time it takes to measure INL and DNL.
Using either the ramp or sine wave histogram test approach, it is necessary to apply an input voltage that slowly progresses past each decision level, producing, on average, at least 16 occurrences, or “hits”, of each output code. So, for example, a 12-bit ADC requires at least 16×2 {circumflex over ( )} 12 full analog-to-digital conversion cycles. The number of hits for each code should ideally be equal, since each step size is ideally equal to all the other step sizes. However, wider codes will produce more hits, while narrow codes will produce fewer hits. The average number of hits per code therefore represents the average step size, or least significant bit (LSB). The histogram is a plot of the number of hits for each code plotted as a function of the code number. Variations in the histogram hit counts are therefore a direct measurement of the non-uniformity of the individual step sizes.
An alternative prior-art technique is to use an external servo circuit, which adjusts the ADC input voltage up or down until a desired output code is achieved as shown in FIG.
1
. This test methodology is also slow, since the servo process takes many full ADC conversion cycles to converge to each decision level.
SUMMARY OF THE INVENTION
The present invention reduces the time required to measure the INL and DNL performance of ADCs by shortening the successive approximation algorithm of the ADC. The invention advantageously comprises a method that reconfigures an ADC under test into a DAC. However, instead of performing a full conversion and comparing the final digital output with a desired output code, the desired target code is written directly to an ADC SAR register or to a dedicated test mode register. Advantageously, using the test mode of the present invention, the ADC does not perform a successive approximation conversion. Instead, the SAR control logic simply writes the desired code to a successive approximation DAC which forms a part of the ADC. A comparator compares the input voltage against the SAR DAC voltage. A servo integrator is then ramped up or down by the SAR logic, depending on the comparison result. Therefore, the ADC can make a single quick comparison to determine which direction the servo integrator should ramp. This is a much faster process than the prior art servo technique which requires a full ADC successive approximation conversion cycle before the ramp-up/ramp-down decision can be made.


REFERENCES:
patent: 4775852 (1988-10-01), Sloane
patent: 5006852 (1991-04-01), Goto et al.
patent: 5252976 (1993-10-01), Miho et al.
patent: 5578935 (1996-11-01), Burns
patent: 6211803 (2001-04-01), Sunter
patent: 6243034 (2001-06-01), Regier
patent: 6268972 (2001-07-01), Philpott et al.
patent: 6329938 (2001-12-01), Spaur et al.
patent: 6351231 (2002-02-01), Price et al.

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