Design flow checker

Data processing: database and file management or data structures – Database design – Data structure types

Reexamination Certificate

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Details

C707S793000, C707S793000

Reexamination Certificate

active

09769004

ABSTRACT:
A method is disclosed for operating a computer system in order to validate data stored in a plurality of data files in a database. Each of the data files have an associated file type and are arranged in a plurality of data stores in the database. At least one of the data files is a data dependent file which contains data dependent upon data in one or more other files of the data store. The method includes the steps of selecting a file locator which is associated with a respective one data store in the database, via the selected file locator identifying a first dependent file and identifying one or more other files on which said first file is dependent. For each identified file a first file reader is selected which is associated with the file type of the identified file. Via each selected first file reader a predetermined parameter of the identified file is determined. The method further includes the steps of comparing the predetermined parameter from the first file with that from the or each other file and responsive to the comparison step providing an output signal for each data file indicating whether the data file is valid.

REFERENCES:
patent: 4667290 (1987-05-01), Goss et al.
patent: 5138713 (1992-08-01), Loten
patent: 5361357 (1994-11-01), Kionka
patent: 5778390 (1998-07-01), Nelson et al.
patent: 6061758 (2000-05-01), Reber et al.
patent: 6369709 (2002-04-01), Larson et al.
patent: 0 911 736 (1999-04-01), None
Wall et al. Generatign verifiable microprosessrs state machine code with HDL Design Tools, Industrial Electronics society, vol. 3, p. 2441-2446, Nov. 2-6, 2003.
Pflanz et al. On-line detection and correction in storage elements with cross-parity check, On-line Testing Workshop, pp. 1-5, Jul. 8-10, 2002.
Vanbekbergen et al. A design and validation system for asynchronous circuits, Annual ACM IEEE Automation Conference, p. 725-730, 1995.□□.
Ahdoot et al. IBM FSD VLSI chip desgin methodogy, Annual ACM IEEE Desgin Automation Conference, pp. 39-45, 1983.
Pandey et al. Formal verification of PowerPC arrays using symbolic trajectory evaluation, Annual ACM IEEE Desgin Confrence, p. 649-654, 1996.
Donald J. McGinnis Autocheck program, program to check vlidity of printed circuit cards and circuit, ACM/CSC-ER, Proceeding of the ACM annual confernce, vol. 1, p. 398-420, year2 1972.
Kern et al. Formal verification in hardware desgin: a survey, ACM Transactions on Design Automation of Electronic System (TODAES), vol. 4, Issue 2, pp. 123-193, 1999.
Michel Dubois,Memory Access Dependencies in Shared-Memory Multiplexers, IEEE Transactions on Software Engineering, vol. 16, No. 6, Jun. 1990, pp. 661-673.
Michael Dubois,Memory Access Dependencies In Shared-Memory Multiplexers, IEEE Transactions on Software Engineering, vol. 16, No. 6, Jun. 1990, pp 661-673.

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