Design-based reticle defect prioritization

Details Design-based reticle defect prioritization Design-based reticle defect prioritization

1999-12-23

2004-08-17

Bali, Vikkram (Department: 2623)

Image analysis

Applications

Manufacturing or product inspection

C382S145000

Reexamination Certificate

active

06778695

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to inspection of reticles for use in manufacturing integrated circuits. More particularly, the invention relates to use of circuit designs (e.g., netlists, layouts) in inspecting reticles for use in manufacturing integrated circuits.
BACKGROUND OF THE INVENTION
FIG. 1
is one embodiment of an integrated circuit processing arrangement. The general uses of the components of
FIG. 1
are known in the art. Light source
100
provides light towards wafer
130
. Mask/reticle
110
blocks light for certain predetermined portions of wafer
130
. Stepper/scanner
120
directs the patterns of mask/reticle
110
to one of multiple integrated circuits being developed on wafer
130
.
High-level integrated circuit (IC) description languages such as VHDL and Verilog® are commonly used to design circuits. One embodiment of VHDL is described in greater detail in “IEEE Standard VHDL Language Reference Manual,” ANSI Std. 1076-1993, Published Jun. 6, 1994. One embodiment of Verilog® is described in greater detail in IEEE Standard 1364-1995. These high-level IC description languages allow a circuit designer to design and simulate circuits by using high-level code to describe the structure and/or behavior of the circuit being designed.
The integrated circuit design is used to generate an IC layout. Verification and other procedures can also be performed on the IC design or the IC layout. A set of reticles are created based on the IC layout and the reticles are used to manufacture the IC. Prior to mass production of the IC, the reticles are inspected to determine whether the IC manufactured from the reticles will perform the desired function. At least one reticle is generated for each layer of the IC to be manufactured.
FIG. 2
illustrates a prior art approach to reticle inspection. The high-level IC description language code is used to produce netlist
200
that describes an interconnection of circuit components that provide the desired functionality. Netlist
200
can include coordinate information to describe the position of various circuit components within the overall circuit. Netlist
200
can then be used to develop the layout and ultimately fabricate an integrated circuit IC having the functionality of the designed circuit. Netlist
200
can also be used for emulation and/or verification purposes.
Netlist
200
is used to generate layout
210
, which describes the physical layout of an IC. Verification tool
220
can compare layout
210
to netlist
200
to verify that layout
210
is an accurate representation of netlist
200
. Layout
210
can be modified as necessary based on results generated by verification tool
220
.
Layout
210
is used to generate reticle database
230
, which is used to generate reticle
240
. Reticle production equipment (not shown in
FIG. 2
) generates reticle
240
from reticle database
230
in any manner known in the art. This can include exposure to electron beams, laser beams, or ion beams using mask writing tools such as, for example, the MEBES 4500 or ALTA 3500 available from ETEC Corporation of Hayward, Calif.
Once fabricated, reticle
240
is then inspected for defects using inspection device
250
. Inspection device
250
can be, for example, Model 351 Inspection System, manufactured by KLA-Tencor of San Jose, Calif. Several techniques for identifying defects are known in the art that typically compare the image of a reticle under inspection with a reference image. The reference image can be, for example, an adjacent identical layout (die:die, or die-to-die inspection), or a reference image derived from the layout (die:database, or die-to-database inspection). In either case, mismatched geometries are flagged as a defect. In either case, defects identified by inspection device
250
are output as defect list
260
. Defect list
260
can also be referred to as an inspection report.
In a typical prior art reticle inspection system, inspection device
250
flags defects based solely on a mismatch of feature geometries between the image and the database pattern. Defect list
260
is then reviewed by a human operator, who examines the image of each defective location on the reticle and classifies the defect. From the classification, the operator determines which defects are insignificant and which require repair. Defect list
260
may be prioritized by the human operator, for example, by size of defect. Defects are repaired at
280
in any manner known in the art.
The reticle inspection and repair technique of
FIG. 2
is also generally human labor intensive and therefore expensive. As integrated circuits become smaller and smaller, the potential for defects increases and the percentage of defects that must be repaired increases, which results in more work for the human operator and a greater expense to manufacture an operable integrated circuit. In other words as the size of an IC decreases and/or the number of layers of the IC increases, the cost of reticle inspection increases.
A prior art solution to this is to prioritize the defects and eliminate the insignificant defects from the defect list using simulation. In this case, the effect the defect will have on the IC is simulated using conventional simulation techniques, and the defects are prioritized by the effective size on the wafer. However, this solution is not ideal. The amount of time for an accurate simulation can be larger than for human review, and all defects must be simulated to allow the prioritization to occur. As the number of defects increases with smaller feature size, this can potentially increase the total time required for defect evaluation.
What is needed is an improved reticle inspection and repair technique that results in decreased simulation requirements and/or faster defect evaluations, while still accurately identifying all defects that will impact the device being fabricated.
SUMMARY OF THE INVENTION
Methods and apparatuses for netlist based reticle defect prioritization are described. A defect list is generated in response to an inspection of a reticle for use to manufacture an integrated circuit. The defect list is compared to a processed netlist corresponding to the integrated circuit and/or a processed layout corresponding to the integrated circuit. The defect is prioritized based, at least in part, on the comparison.
In one embodiment, the processed netlist provides a device location that can be used to identify regions of interest to be used for prioritization of the defect list. For example, a predetermined region around a transistor gate can be defined as a region of interest. In one embodiment, the processed layout provides device geometry and/or critical dimensions that can be used to identify regions of interest to be used for prioritization of the defect list.


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patent: 4758094 (1988-07-01), Wihl et al.
patent: 5598341 (1997-01-01), Ling et al.
patent: 5686206 (1997-11-01), Baum et al.
patent: 5994030 (1999-11-01), Sugihara et al.
patent: 6483937 (2002-11-01), Samuels
patent: 04 340740 (1992-11-01), None
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patent: WO00/36525 (2000-06-01), None
International Seach Report, European Patent Office, Date of Mailing: May 7, 2002, International application No.: PCT/US 00/42830, International filing date: Dec. 22, 2000, pp. 1-4.

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