Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Using structure alterable to conductive state
Reexamination Certificate
2001-05-21
2003-07-15
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Using structure alterable to conductive state
C438S113000, C438S467000, C438S600000, C438S643000, C257S530000
Reexamination Certificate
active
06593172
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to the general field of integrated circuits with particular reference to programmable circuitry based on antifuses.
BACKGROUND OF THE INVENTION
To meet the needs of customers who wish to manufacture small volumes of custom chips without the delay and expense of going to a foundry, field programmable chips such as PLAs (programmable logic arrays) and PGAs (programmable gate arrays) have been available for some time. Personalization may be effected dynamically (by means of pass transistors) enabling a chip to be personalized many times or a write-once technology may be employed (with an attendant improvement in circuit density and speed). Implementation of write-once personalization may be accomplished by either breaking existing connections or by forming new ones.
The element that enables the formation of new connections is the antifuse. This is a connection between two layers of metal made through a via which includes in its serial path a layer of material that, as initially deposited has relatively high resistivity. When its temperature is raised above some critical value this material undergoes a phase change which causes its resistivity to drop by several orders of magnitude. Said phase change is commonly (though not necessarily) a change from an amorphous to a crystalline state. The necessary heating is most conveniently effected by passing a suitable current pulse through the afore-mentioned via.
Since the via that contains the layer of antifuse material is similar to the standard vias routinely used for connecting between wiring layers it has been the practice of the prior art to form both via types in a single operation. Referring now to
FIG. 1
, we show there, in schematic cross-section, a substrate
11
(typically the upper portion of an integrated circuit) on whose topmost surface a first layer of metal
12
(M1) has been deposited. Layer
12
is coated with titanium nitride layer
13
which will serve as a barrier layer. Dielectric layer
14
lies over layer
13
and, as can be seen, two via holes (
16
and
17
), that pass through it have been simultaneously formed, and then lined with amorphous silicon layer
15
which will be used as the antifuse material. To protect the antifuse layer, a protective coating
15
a
of titanium and titanium nitride is then immediately deposited.
The next step in the prior art process is illustrated in
FIG. 2
where amorphous silicon layer
16
has been selectively removed from everywhere except inside, and close to, via hole
17
. It is difficult to create a plasma etch process that will remove amorphous silicon material from features with aspect ratios of the order encountered in a via while still maintaining the critical dimensions of the masked feature overlying the antifuse via.
Should any material from layer
15
or
15
a
be left behind in via hole
16
, a high contact resistance between the two metal layers that are connected by that via will be introduced. If over-etching is done in an attempt to remedy this, there is a danger that the overlap of the amorphous silicon layer over the via hole
17
will be reduced, causing damage to the resulting antifuse structure.
Previously, antifuses were not isolated individually. This cause problems during metal
2
(M2) etch where two layers of titanium and titanium nitride, as well as the amorphous, all needed to be simultaneously etched. Incomplete etching at this stage can cause metal shorting.
The present invention discloses a solution to the above problems.
A routine search of the prior art was performed with the following references of interest being found:
U.S. Pat. No. 6,159,836 (Wei) shows a TiN/&agr;Si/TiN sandwich anti-fuse structure. U.S. Pat. No. 5,789,795 (Sanchez et al.), U.S. Pat. No. 5,573,970 (Pramanik et al.), and U.S. Pat. No. 6,107,165 (Vain et al.) all show related anti-fuse structures, some with etch stops.
SUMMARY OF THE INVENTION
It has been an object of the present invention to provide a process for manufacturing both an antifuse and a standard via.
A further object has been that said process permit over-etching of the standard vias, as needed.
Another object has been that the process allow close control of the thickness of the antifuse layer.
Still another object has been that the antifuse be fully encapsulated and isolated from other antifuse structures.
These objects have been achieved by first forming only the antifuse via. This allows etch time to be optimized. Overetch into the titanium nitride layer can cause antifuses to short to underlying metal. Underetch can render the antifuse unprogrammable if dielectric remains in the via. In addition, the antifuse material may be patterned without regard to possible side effects on the standard vias. The latter are then formed, without (as in the prior art) any concerns that the antifuse may be affected. Furthermore, these standard vias may be overetched in order to clear the thick titanium nitride layer and to ensure good electrical contact and low via resistance. The result is an antifuse that is well isolated from other antifuses and a standard via that will facilitate good electrical contact between metal layer
1
and
2
.
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International Rectifier Corporation
Luu Chuong A
Ostrolenk Faber Gerb & Soffen, LLP
Smith Matthew
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