Design and layout techniques for low parasitic capacitance...

Details Design and layout techniques for low parasitic capacitance... Design and layout techniques for low parasitic capacitance...

2006-08-15

2006-08-15

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified configuration

C257S734000, C257SE23144

Reexamination Certificate

active

07091617

ABSTRACT:
A semiconductor device that reduces the parasitic capacitance between a conductive trace and a substrate, and a method of fabricating the same. The semiconductor device includes a substrate, an insulator layer disposed upon the substrate, a conductive trace disposed upon the insulator layer, and an element disposed between the substrate and the conductive trace. A first capacitance exists between the conductive trace and the substrate and a second capacitance results between the conductive trace and the substrate due to the presence of the element. The second capacitance is in series with the first capacitance, thereby reducing an effective capacitance between the conductive trace and the substrate.

REFERENCES:
patent: 5027174 (1991-06-01), Mimoto
Wolf,“Silicon Processing for the VLSI Era, vol. 3—The Submicron MOSFET,” 1995, Lattice Press, vol. 3, p. 323-324.

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