Design aiding apparatus and method for designing a semiconductor

Details Design aiding apparatus and method for designing a semiconductor Design aiding apparatus and method for designing a semiconductor

1996-12-09

2000-02-15

Teska, Kevin J.

Boots, shoes, and leggings

364489, 364490, 364491, 382145, G01R 19145

Patent

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06024478&

ABSTRACT:
An electric work station calculates an output load of a selected cell based on information from at least one of a design cell information library, a logic circuit information library and a layout information library. The work station further calculates a hot carrier dependent lifetime of a transistor in the cell by using the computed output load and information from a reliability information library, and verifies reliability of the cell by comparing the calculated lifetime with a reference value.

REFERENCES:
patent: 5539652 (1996-07-01), Tegethoff
patent: 5606518 (1997-02-01), Fang et al.
patent: 5737580 (1998-04-01), Hathaway et al.
K. N. Quader et al, "A Bidirectional NMOSFET Current Reduction Model for Simulation of Hot-Carrier-Induced Circuit Degradation", IEEE Transactions of Electron Devices, vol. 40, No. 12, Dec. 1993, pp. 2245-2253.
Shiuh-Luen Wang, et al., Solid-State Electronics, vol. 36, No. 6, pp. 833-841, "Rely: A Physics-Based CAD Tool For Predicting Time-Dependent Hot-Electron Induced Degradation In Mosfet's", 1993.

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