Coded data generation or conversion – Digital code to digital code converters – Serial to parallel
Reexamination Certificate
2000-05-01
2003-09-30
Young, Brian (Department: 2633)
Coded data generation or conversion
Digital code to digital code converters
Serial to parallel
C341S101000, C370S535000
Reexamination Certificate
active
06628214
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a serial-to-parallel conversion apparatus, a semiconductor device, an electronic device, and a data transmission system, and more particularly to an apparatus for transmitting digital image information from an information processing apparatus to a device such as a liquid crystal display, a large-size high-resolution flat panel display, a liquid crystal projector, or a multi-display system.
2. Description of Related Art
A data transmission system for transmitting image information such as that shown in
FIG. 16
is known in the art. In such a system, it is known to use one or more pairs of wires as transmission means for transmitting digital image information to a display device. This technique is called LVDS (low voltage differential signal) transmission.
In the data transmission system shown in
FIG. 16
, data is transmitted from one information processing apparatus
500
to another information processing apparatus
600
via an LVDS cable.
In a transmitting apparatus, parallel data
513
such as image information output from the information processing apparatus
500
at the transmitting end is converted into serial data
514
by a parallel-to-serial converter
520
in accordance with a clock signal CL
511
produced by a PLL
530
by way of multiplying the frequency of a dot clock signal CL
510
.
The resultant serial data
514
is transmitted together with a clock signal CL
512
similar to the dot clock signal CL
510
via drivers
540
(
540
-
1
,
540
-
2
, . . . ), a cable
560
, and receivers
630
(
630
-
1
,
630
-
2
, . . . ).
In accordance with a clock signal CL
602
generated by a PLL
620
by way of multiplying the frequency of a clock signal CL
601
similar to the clock signal CL
512
, a serial-to-parallel converter
610
converts the serial data
604
to parallel data
605
and supplies the resultant parallel data
605
to the information processing apparatus
600
.
In the case where the cable comprising one or more pairs of wires, the dot clock signal CL
510
(
512
,
601
,
603
) and the coded serial data
514
(
604
) are transmitted, while in the receiving apparatus the clock signal CL
602
is generated by multiplying the frequency of the dot clock signal CL
601
and the serial data is reconverted to parallel data in accordance with the obtained clock signal CL
602
.
When serial data is converted to parallel data, it is required to detect boundaries (start positions of respective data strings) between two adjacent data strings of the serial data. As can be seen from
FIG. 18
, information used to detect the boundaries is given by the clock signal CL
601
(CL
510
, CL
512
). Because one cycle of the clock signal CL
601
corresponds to the length of one unit data string, the timing of each rising edge (or falling edge) of the clock signal CL
601
has a particular relation with the start position of a data string of the serial data
604
. Therefore, the start position of each data string of the serial data
604
can be detected by detecting a rising edge (or falling edge) of the clock signal CL
601
, and thus it is possible to convert serial data to parallel data without producing a bit position error.
However, the dot clock signal CL
510
output from the information processing apparatus
500
often has large jitter which affects extraction of the clock signal or multiplication of the dot clock signal performed in the receiving apparatus and thus causes a failure in conversion to parallel data or in reproduction of data.
That is, as shown in
FIGS. 16 and 18
, when parallel data (A
0
), . . . , (Ak) are input to the parallel-to-serial converter
520
via parallel data input terminals Txin
0
-Txink, the parallel-to-serial converter
520
sequentially samples the parallel data (A
0
), . . . , (Ak) from data to data in synchronization with the clock signal CL
511
generated by means of frequency multiplication thereby converting them into serial data (A
0
. . . Ak).
The resultant serial data (A
0
. . . Ak) is output together with the dot clock signal CL
510
from the driver
540
and transmitted via the LVDS cable
560
.
The serial data (A
0
. . . Ak)
604
is then input, as shown in
FIGS. 16 and 18
, to the serial-to-parallel converter
610
via the serial data input terminal Rxin and sampled in synchronization with the clock signal CL
602
generated by way of frequency multiplication.
As described above, because the start position of the serial data (A
0
. . . Ak) can be detected from the timing of a rising edge (or falling edge) of the clock signal CL
601
, it is possible to output the parallel data (A
0
), . . . , (Ak) so that A
0
corresponds to Rxout
0
and A
1
corresponds to Rxout
1
.
If jitter occurs in the clock signal CL
510
, a phase difference occurs between the clock signal CL
511
multiplied in the transmitting apparatus and the clock signal CL
602
multiplied in the receiving apparatus, as shown in
FIG. 19
, and thus the serial-to-parallel converter
610
cannot perform a correct conversion upon the parallel data converted into serial form by the parallel-to-serial converter
520
. The term “jitter” is generally used to describe a waveform disturbance such as that shown in FIG.
19
.
More specifically, referring to the timing chart of
FIG. 17
illustrating the relationship among the serial data
604
, the parallel data
605
, and CL
602
(multiplied signal) in the serial-to-parallel converter
610
, jitter causes a deviation between the timing of the clock signal CL
601
or
602
and the start position of the nth data string of the serial data. Such a deviation can cause incorrect detection of a boundary between adjacent data strings (the start position of a data string) of the serial data.
The major cause of the above problem is in that the serial-to-parallel converter
610
performs the converting operation in synchronization with the clock signal CL
602
multiplied by the PLL
620
.
In the parallel-to-serial converter
520
, the clock signal
511
is generated by the PLL
520
by way of frequency multiplication, while in the serial-to-parallel converter
610
the clock signal
602
is generated by the PLL
620
by way of frequency multiplication. Therefore, if the clock signal
510
includes jitter, a timing deviation between the clock signals
511
and
602
occurs as shown in FIG.
19
. When there is such jitter, if the serial data
604
generated on the basis of the multiplied clock signal
511
is sampled in synchronization with the clock signal
602
, the resultant parallel data may be incorrect.
The phase error generated by the jitter can cause an incorrect detection of a signal level. For example, a signal level which should be determined as a low level may be incorrectly determined as a high level. As a result, it becomes difficult or even impossible to correctly read the content of data. That is, because the serial-to-parallel conversion is performed on the basis of the out-of-synchronization clock signal, data may be incorrectly converted into parallel form. For example, data which should be converted to R
0
, G
0
, and B
0
may be incorrectly converted to G
0
, B
0
, and R
1
.
Furthermore, in order that a VCO (voltage controlled oscillator) of the PLL can operate in a stable fashion, it is required that the voltage of a power supply should be stable enough. However, in general, fluctuations of the voltage of the power supply occur owing to noise in a logic circuit or the like, and thus the operation of the PLL become unstable. For the above reasons, use of two PLLs, one in the transmitting apparatus and the other in the receiving apparatus, results in a reduction in a margin for correct reception of data. Furthermore, in order that each PLL operates in a stable fashion, it is required that the power supply voltage should be stabilized over the entire apparatus. This results in an increase in cost.
SUMMARY OF THE INVENTION
In view of the above problems, it is an object of the present invention to provide a serial-to-parallel co
Kawase Takeo
Kitamura Shojiro
Nguyen John B
Oliff & Berridg,e PLC
Seiko Epson Corporation
Young Brian
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