Descriptor write back delay mechanism to improve performance

Details Descriptor write back delay mechanism to improve performance Descriptor write back delay mechanism to improve performance

2003-10-14

2008-10-21

Kizou, Hassan (Department: 2619)

Multiplex communications

Pathfinding or routing

Switching a message which includes an address header

C370S428000, C370S429000

Reexamination Certificate

active

07440469

ABSTRACT:
A multiprocessor switching device substantially implemented on a single CMOS integrated circuit is described in connection with a descriptor write back timer mechanism for use in efficiently writing descriptors back to memory after transmitting data under control of the descriptors to inform the processor(s) about system-related functions for a plurality of channels. A timing interval pulse is provided for prompting descriptor write back operations that are otherwise subject to a minimum descriptor count requirement.

REFERENCES:
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patent: 6987768 (2006-01-01), Kojima et al.
patent: 7012926 (2006-03-01), Weng et al.
patent: 7272147 (2007-09-01), Hazama

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