Cryptography – Video cryptography – Video electric signal modification
Reexamination Certificate
1998-02-03
2002-06-18
Barron, Jr., Gilberto (Department: 2767)
Cryptography
Video cryptography
Video electric signal modification
C380S215000, C380S261000, C380S227000, C380S001000, C713S152000
Reexamination Certificate
active
06408077
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the invention
The invention relates to a security element allowing the processing of a digital data stream.
More particularly, the invention relates to a descrambling device contained in a security element such as that mentioned above.
The security element according to the invention can, for example, be a smart card of a conditional access system and the digital data can be video data.
2. Description of the Related Art
As is known to a person skilled in the art, a conditional access system enables a service provider to supply his services only to those users who have acquired entitlements to these services. Such is the case, for example, in pay television systems.
The item supplied by the service provider is an item scrambled by control words. The scrambled item can only be descrambled, and hence read by the user, in line with the entitlements allocated to this user. So as to afford access to his service only to those users who are authorized, the service provider supplies them with a smart card and a decoder.
The circuits for descrambling the item are contained either in the smart card or in the decoder.
The present invention relates equally well to the case in which the circuits for descrambling the item are in the smart card and the case in which the circuits for descrambling the item are in the decoder.
Generally, the digital data to be descrambled are transmitted to the descrambling device in the form of data packets made up of bits in series.
By way of example, in the case of a smart card according to the NRSS standard (standing for “National Renewable Security Standard”), the data packets are made up of video data of 188 or 131 bytes of 8 bits and the bit frequency of the video data is a frequency of high value, for example equal to 50 MHz. As is known to a person skilled in the art, the data packets may follow one another with no discontinuity or be separated by any number of bit periods.
Before being descrambled, the serial video data are grouped as binary combinations of 64 bits.
On account of the time taken by the operation for descrambling the 64-bit combinations, the data to be descrambled transmitted to the smart card are stored in a shift register so long as the descrambling of the current data is still in progress.
According to the prior art, the working frequency of the logic circuits which make it possible to construct the binary combinations to be descrambled is the bit frequency.
The abovementioned logic circuits are circuits built using CMOS technology (“Complementary Metal Oxide Semiconductor”). As is known to a person skilled in the art, the power consumed by CMOS technology circuits is proportional to their working frequency. Typically, for a smart card which complies with the NRSS standard, the power dissipated by the logic circuits which control the entire descrambling operation is of the order of 400 mW.
This value of the power consumed is high and has numerous drawbacks. It gives rise to mediocre reliability of the descrambling device and limits the range of temperatures in which the security element can be used.
SUMMARY OF THE INVENTION
An object of the invention is to provide a descrambling device for a security element which does not have the abovementioned drawbacks.
To this end, the invention relates to a device for descrambling digital data comprising, in series, an input circuit making it possible to form combinations of serial digital data which it receives in time with a clock signal CLK, a descrambling circuit making it possible to descramble the combinations of data arising from the input circuit and an output circuit making it possible to transform into serial digital data, in time with the clock signal CLK, the descrambled combinations of data arising from the descrambling circuit. According to the invention the input circuit comprises first means making it possible for the combinations of data to be constructed in time with a clock signal CL
1
whose frequency is equal to a fraction of the timing of the clock signal CLK, the output circuit comprises second means making it possible for the descrambled combinations of data arising from the descrambling circuit to be split up into sub-combinations of data in time with a clock signal CL
2
with the same frequency as the signal CL
1
and the descrambling device comprises a synchronization and control device which generates the clock signals CL
1
and CL
2
.
By virtue of the invention, the number and surface area of the circuits of the descrambling device working at the bit frequency are thus reduced.
An advantage of the invention is to decrease the power dissipated by the descrambling device.
According to a particular embodiment, the input circuit comprises, in series, a deserializer making it possible to transform the said serial digital data into combinations of n bits and the said first means making it possible to associate the combinations of n bits as blocks of combinations of m×n bits constituting the said combinations of data, and the output circuit comprises, in series, the said second means making it possible to split up the said descrambled combinations of data into m sub-combinations of n bits and a serializer making it possible to recover the descrambled data of each sub-combination of n bits.
According to a preferred aspect of the invention, the said first means comprise a first FIFO-type memory with clock signal CL
1
and the said second means comprise a second FIFO-type memory with clock signal CL
2
.
According to a particular embodiment, the device of the invention comprises means such that the descrambling circuit possesses a transparent mode for which the data combinations which it receives are not descrambled.
According to a particular embodiment, the digital data received as input are grouped into successive data packets and the frequency of the clock signals CL
1
and CL
2
is equal to the frequency of the clock signal CLK divided by n and the clock signal CL
2
is shifted in phase with respect to the signal CL
1
in such a way as to take into account the number of bit periods which separate two successive data packets.
The invention also relates to a security element comprising a device for descrambling digital data, such as described above.
According to an aspect of the invention, the said security element is a smart card of a conditional access system.
The invention also relates to a digital decoder comprising a device for descrambling digital data, such as described above.
In the remainder of the description, the digital data taken by way of example are video data. However, more generally, the invention relates to any type of digital data, as was mentioned earlier.
Other characteristics and advantages of the invention will emerge on reading a preferred embodiment given with reference to the appended figures in which:
REFERENCES:
patent: 4139839 (1979-02-01), Engel et al.
patent: 2257557 (1993-01-01), None
patent: WO96/06504 (1996-02-01), None
Barron Jr. Gilberto
Jack Todd
Shedd R. D.
Shoneman D. T.
Thomson Licensing SA.
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