Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2001-02-26
2001-10-23
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Floating gate
Particular biasing
C365S185170, C365S185180, C365S185190, C365S185030, C365S168000, C365S189090, C365S189050, C365S196000, C365S195000
Reexamination Certificate
active
06307783
ABSTRACT:
BACKGROUND
The present invention relates generally to memory devices. More particularly, the present invention relates to a descending staircase read technique for a multi-level cell NAND flash memory device.
A variety of semiconductor memory devices have been developed for storage of information. Examples include volatile and nonvolatile memory. Nonvolatile memory provides a key advantage in that it retains stored data after power is removed from the device. One example of nonvolatile memory is flash memory. However, manufacture and operation of nonvolatile memory is generally more complex than for volatile memory. For all memory devices, important design goals include increased storage density and reduced read and write times.
A conventional memory device includes an array of storage cells or memory cells. Each cell stores a single binary digit or bit of information. For example, in a flash memory, the threshold voltage of a transistor in the memory cell is adjusted according to the data stored. During a read cycle, the threshold voltage is sensed to resolve the state of the data stored. In a conventional binary memory, this data is conventionally described as having a state of logic 0 or logic 1. The array of storage cells is surrounded by circuits for reading and writing data and controlling operation of the memory device.
Recently, multi-level cells have been developed. Multi-level storage refers to the ability of a single memory cell to store or represent more than a single bit of data. A multi-level cell may store 2, 4, 8. . . etc., bits in a single storage location.
Multi-level cell devices provide a substantial advantage by exponentially increasing the storage capacity of a memory device. However, multi-level cell devices present several challenges for developing circuit designs to access the memory cells. One such challenge is reliably and rapidly reading the data stored in a multi-level storage cell.
BRIEF SUMMARY
By way of introduction only, a multi-level memory includes an array of memory cells accessible through respective word lines and bit lines, a control circuit controlling embedded operations of the memory and a read voltage generating circuit to generate a descending staircase read voltage to a word line associated with a selected memory cell under control of the control circuit. The multi-level memory further includes a read circuit including a latch circuit, and a switch circuit responsive to an evaluate/enable signal to selectively store a read state signal in the latch circuit in response to a sense signal generated from application of the descending staircase read voltage to the word line associated with the selected memory cell.
The foregoing discussion of the preferred embodiments has been provided only by way of introduction. Nothing in this section should be taken as a limitation on the following claims, which define the scope of the invention.
REFERENCES:
patent: 5761118 (1998-06-01), Chai
patent: 5973959 (1999-10-01), Gerna et al.
patent: 6166951 (2000-12-01), Derhacobian et al.
Brian Dipert and Lou Herbert, Intel Corp., “Flash Memory Goes Mainstream”, IEEE Spectrum, Oct. 1993, pp. 48-54.
AMD Utilizing UltraNAND Product Brief, “64 Megabit Mass Storage Flash Memory-Utilizing NAND Technology”, found at web site http://www.amd.com/products
vd/overview/ultranand/22294.html.
Advanced Micro Devices , Inc.
Tran Andrew Q.
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