Deriving statistical device models from electrical test data

Details Deriving statistical device models from electrical test data Deriving statistical device models from electrical test data

1999-04-12

2003-05-06

Broda, Samuel (Department: 2123)

Data processing: structural design, modeling, simulation, and em

Modeling by mathematical expression

C703S001000, C700S121000, C438S014000

Reexamination Certificate

active

06560568

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to techniques for deriving statistical device models for mass-produced products such as semiconductor chips.
2. Description of the Related Art
During the mass manufacture of various products, such as semiconductor chips or systems having integrated circuits (ICs), failures can occur in some of the chips produced, i.e., some of the chips are defective. For example, in mass-producing semiconductor chips, chip-to-chip variations, sometimes referred to as interdie variations, can be introduced during the fabrication process. If these variations are too far from the ideal or nominal for a given chip, the chip may not function properly because various key circuit-level performance metrics may vary too much from the maximum tolerable limits.
The individual units of the product which is mass produced may be sometimes referred to herein as chips. Chips are formed in the substrate of a physical wafer. Typically, several chips are formed in each wafer. A set of wafers that are processed together is called a lot. A wafer is a very thin, flat disc typically about 8-12″ in diameter at the present time. The manufacturing process consists of operations on the surface and substrate of the wafer to create a number of chips. Once the wafer is completely processed, it is cut up into the individual chips, which are typically about half inch by half inch in size. A lot is thus a mass-produced set of chips or units, each of which is supposed to conform to an ideal design within certain tolerable limits.
Inevitable variations in the manufacturing process can give rise to interdie variations, which can be more or less severe depending upon the particular manufacturing process as well as upon the particular design of the product to be mass-produced. The number of chips that satisfy all performance specifications from a lot determine the parametric yield of the design and manufacturing process used with a given target foundry for mass producing the chip. Each chip comprises an IC or system which itself comprises a network of several circuit-level elements such as operational amplifiers (op amps) and the like. All of these circuit-level elements are composed of so-called compact or primitive “devices,” which are characterized by various compact or primitive model-level parameters. For example, a device may be a transistor or portions thereof, from which larger or more complex structures like op amps are composed. A chip thus comprises a circuit or system which comprises a network of circuit-level elements, which are themselves formed from the compact devices.
The technique of worst-case files is often used in order to model the interdie variations in a manner that is useful for circuit designers. Worst-case files represent a number of cases that include the nominal case and also various extreme cases, each of which consists of device model parameters corresponding to a particular “processing corner.” Collectively, the worst-case files represent the nominal and various extremes of device behavior corresponding to the variations of a particular manufacturing process. The use of worst-case files is described in C. Michael & M. Ismail,
Statistical Modeling for Computer
-
Aided Design of MOS VLSI Circuits,
Kluwer Academic Publishers, Boston/Dordrecht/London, 1992 and in D. Foty,
MOSFET Modeling with Spice,
Prentice Hall, Upper Saddle River, N.J., 1997.
Obviously, a higher parametric yield is desirable so that more working chips are produced in each given lot. Worst-case files are thus used by chip designers to try to achieve high parametric yield. The widths and lengths of the various primitive devices may be adjusted, by repeated simulations and/or experimentation, to achieve a high percentage of chips that are expected that satisfy the worst-case limits. Designs that are predicted to work satisfactorily when simulated with worst-case files can be expected to have high parametric yields. Thus, by adjusting the sizes (widths and lengths) of the various primitive devices and verifying via simulation with the worst-case files that the performance is satisfactory, a high parametric yield can be expected from the resulting design.
Thus, a given circuit is designed and laid out by using worst-case files. The performance of the circuit design may then be simulated for the nominal case, to ensure it satisfies the key performance metrics. The performance for other cases of interdie variation may also be checked to see if all or most of them satisfy the desired key performance metrics. If all or most (to a certain specified percentage) of these cases also perform satisfactorily, then a high parametric yield can be expected since the worst-case interdie variations (variations in important or selected circuit performance metrics) caused by manufacturing variations will still allow the circuit to perform satisfactorily. These and other aspects of using worst-case files are discussed in the Michael & Ismail text and in D. Foty,
MOSFET Modeling with Spice,
Prentice Hall, Upper Saddle River, N.J., 1997.
Such an approach may be feasible for a circuit whose specifications are not very aggressive and whose performance is not very sensitive to interdie variations. Such circuits may be “over-designed” for the nominal case so that circuit performance is still satisfactory even when there is deviation from the nominal case for many or all of the circuit performance metrics. This can result in a circuit design expected to provide satisfactory performance even at all the extreme cases.
However, the worst-case file or “case-based simulation” approach is not always feasible or optimal. For example, in some designs a number of complex, competing performance constraints may be specified. These constraints may be satisfied in the nominal case, but different performance criteria would violate their specifications to different degrees in the extreme cases. In such a situation, the case-based simulation approach does not provide the designer with any quantitative feedback on the robustness of the design. In this case, the designer may be forced to over-design or, if this is not feasible, the parametric yield will be unpredictable and possibly too low or too uncertain for economic viability.
The use of statistical device models (also sometimes known as statistical process models) can help to alleviate this problem. Statistical models of semiconductor devices are used to quantitatively assess the key circuit performance metrics which are expected to result from a mass manufacture in a given production process or foundry. In particular, a statistical device model allows one to predict the correlated variations of the relevant performance metrics of the population of chips to be manufactured via a given process. Thus, with a suitable statistical model it is possible to determine, to some degree of accuracy, the standard deviations and correlations of the various performance metrics of the product or system to be manufactured. The statistical device models can also allow one to more accurately determine the percentage of sample circuits that satisfy all the performance specifications, i.e., to predict the expected parametric yield. Thus, for a given schematic layout and IC design, the statistical model can be used to quantitatively assess the manufacturability of the IC design with respect to a target foundry.
Conventional approaches to statistical device modeling include Michael & Ismail; and P. Chatterjee, P. Yang, D. Hocevar & P. Cox, “Statistical Analysis in VLSI Process/Circuit Design,” in
Statistical Approach to VLSI,
ed. S. W. Director & W. Maly, pp. 255-292, North-Holland, 1994. Such approaches typically assume the availability of I-V (current-voltage) measurements on a large number of units. Device model parameters are then extracted for each measured chip using standard parameter extraction techniques. From this database, the correlated distributions of the model parameters are determined and form the basis of further statistical analysis

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