Deriving signal constraints to accelerate sequential test genera

Details Deriving signal constraints to accelerate sequential test genera Deriving signal constraints to accelerate sequential test genera

1997-04-14

1999-02-23

Beausoliel, Jr., Robert W.

Excavating

364488, 364489, G01R 3128

Patent

active

058751963

ABSTRACT:
A method to significantly accelerate sequential test generation algorithms by accurately computing signal constraints for large sequential circuits and using these constraints effectively during deterministic sequential test generation. The signal constraint computation technique is based on three key ideas: (1) unlike prior techniques (which compute line probabilities assuming only a 0 or 1 value for any signal), line probabilities are computed by allowing signals to assume values other than 0 or 1, (2) line justification techniques are employed to update line probabilities, and (3) symbolic simulation is iteratively used in conjunction with line probability computation and line justification to refine the set of values that a signal can assume. The method results in a significant reduction (more than 50%) in test generation time which is achieved without comprising the fault coverage than can be obtained.

REFERENCES:
patent: 5559811 (1996-09-01), Abramovici et al.
patent: 5566187 (1996-10-01), Abramovici et al.
patent: 5602856 (1997-02-01), Teramoto
patent: 5625630 (1997-04-01), Abramovici et al.
patent: 5657240 (1997-08-01), Chakradhar et al.
patent: 5703789 (1997-12-01), Beausang et al.
Fujiwarea, Three valued Neural Networks for test generation, Fault tolerant computing, 1990 Int'l Symp, pp. 64-71.
Magdolen et al., REGGEN-Test generation on register transfer level, European design conference, pp. 259-264, 1993.
Roy et al., The use of RTL description on accurate timing verification and test generation, IEEE journal of solid-state, vol. 26, No. 9, pp. 1230-1239, 1991.
Chakradhar et al., Deriving signal constraints to accelerate sequential test generation, 10th Internal conference on VLSI design, pp. 499494, Jan. 1991.
Liang et al., "Identifying Untestable Faults in Sequential Circuits", IEEE Design & Test of Computers, Fall 1995.

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