Derivation of VT group clock from SONET STS-1 payload clock and

Details Derivation of VT group clock from SONET STS-1 payload clock and Derivation of VT group clock from SONET STS-1 payload clock and

1992-05-21

1998-02-03

Hsu, Alpus H.

Multiplex communications

Pathfinding or routing

Through a circuit switch

370476, 370506, 370535, H04J 300

Patent

active

057152489

ABSTRACT:
A SONET formatter circuit (10) receives a parallel STS-1** TX signal (19) from a highspeed interface module. The STS-1** TX signal (19), which contains a floating VT group payload, is demultiplexed into seven parallel VT groups (33). These seven parallel VT groups (33) are converted to serial by a parallel to serial converter (34) and transmitted serially to lowspeed interface modules as DEMUX direction VT group data signals (42, 43). The SONET formatter circuit (10) also receives serial MUX direction VT group data signals (68, 69) from lowspeed interface modules. These serial VT group data signals (68, 69) are converted to seven parallel VT groups (89) by a serial to parallel converter (64). These seven parallel VT groups (89) are multiplexed with overhead data (84) into a parallel STS-1** RX signal (50) which is transmitted to a highspeed interface module. To maintain continuous VT group frame transmissions, a VT group clock generation circuit (72) is required.

REFERENCES:
patent: 4967405 (1990-10-01), Upp et al.
patent: 5060229 (1991-10-01), Tyrrell et al.
patent: 5091907 (1992-02-01), Wettengel
patent: 5111485 (1992-05-01), Serack
patent: 5131013 (1992-07-01), Choi
patent: 5136587 (1992-08-01), Obana et al.

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