Deposition of amorphous silicon for the formation of interlevel

Details Deposition of amorphous silicon for the formation of interlevel Deposition of amorphous silicon for the formation of interlevel

1987-06-26

1988-05-31

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 46, 437161, 357 59, H01L 2904

Patent

active

047481331

ABSTRACT:
A new and improved method using the deposition of amorphous silicon for the formation of semiconductor memory device interlevel dielectrics. After the deposition of a first polysilicon layer, an amorphous silicon layer is deposited thereon. The polysilicon layer and amorphous silicon layer are etched to form a floating gate. The amorphous silicon layer allows for the growth of thermal oxide layers to take place at lower temperatures thereby decreasing the temperature at which the oxide layers are grown while still repressing the asperity formation. This allows for high quality oxide insulation layers.

REFERENCES:
patent: 4370798 (1983-02-01), Lien et al.
patent: 4420871 (1983-12-01), Scheibe
patent: 4558338 (1985-12-01), Sakata
patent: 4679171 (1987-07-01), Logwood et al.

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