Deposited screen oxide for reducing gate edge lifting

Details Deposited screen oxide for reducing gate edge lifting Deposited screen oxide for reducing gate edge lifting

2000-01-03

2003-02-11

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Repair or restoration

C438S261000, C438S264000, C438S595000

Reexamination Certificate

active

06518072

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to floating gate semiconductor memory devices such as EEPROMs. More specifically, this invention relates to methods of manufacturing floating gate semiconductor memory devices such as EEPROMs. Even more specifically, this invention relates to methods of manufacturing floating gate semiconductor memory devices such as EEPROMs that reduce the amount of gate-edge lifting.
2. Discussion of the Related Art
A class of non-volatile memory devices known as “flash” EEPROM (Electrically Erasable Programmable Read Only Memory) devices combines the advantages of EPROM density with the electrical erasability of an EEPROM. One feature that distinguishes flash EEPROM memory cells from standard EEPROM memory cells is that unlike standard EEPROM memory cells, flash EEPROM memory cells do not contain a select transistor on a one-for-one basis with each floating gate memory cell. A select transistor is a transistor that allows the selection of an individual memory cell within the memory device and is used to selectively erase a specific memory cell. Because flash EEPROMs do not have a select transistor for each floating gate transistor, flash EEPROM memory cells cannot be individually erased and therefore must be erased in bulk, either by erasing the entire chip or by erasing paged groups or banks of cells. Elimination of the select transistor allows for smaller cell size and gives the flash EEPROM an advantage in terms of manufacturing yield (in terms of memory capacity) over comparably sized standard EEPROMs.
Typically, a plurality of flash EEPROM cells is formed on a semiconductor substrate, which is also known as a silicon wafer.
FIG. 1
illustrates a single conventional flash EEPROM memory cell having a double-diffused source region. As shown in
FIG. 1
, flash memory cell
100
is formed on a p-type substrate
110
and includes an n type double-diffused source region
102
and an n+drain region
104
. The drain region
104
and the source region
102
are spaced apart from each other forming a channel region
122
. A source electrode
114
and a drain electrode
112
are connected to the source region
102
and the drain region
104
, respectively.
The double-diffused source region
102
is formed of a lightly doped n region
128
(phosphorous doped) and a more heavily doped but shallower n+region
130
(arsenic doped) embedded within the deep n region
128
. The phosphorus doping within n region
128
reduces the horizontal electric field between the source region
102
and the substrate
110
.
The floating gate
106
is disposed a short distance above the source region
102
, the drain region
104
and the channel region
122
over a dielectric layer
118
, which is also known as a tunnel oxide region. Above the floating gate
106
and disposed over the dielectric layer
116
is a control gate
108
. The dielectric layer
116
is typically formed of an oxide
itride/oxide layer known in the semiconductor manufacturing art as an ONO layer. A control gate electrode
120
is attached to control gate
108
. The dimension L
GATE
132
represents the gate length for the gates contained in flash memory cell
100
.
In a conventional method of operation, the programming of a flash EEPROM memory cell is achieved by inducing “hot electron” injection from a section of the channel
122
near the drain
104
into the floating gate
106
. The injected electrons cause the floating gate
106
to carry a negative charge. Grounding the source region
102
, biasing the control gate
108
to a relatively high positive voltage and biasing the drain region
104
to a moderate positive voltage induce the hot electrons.
For example, to program the flash memory cell
100
, the source electrode
114
is connected to ground, the drain electrode
112
is connected to a relatively high voltage (typically +4 volts to +9 volts) and the control gate electrode
120
is connected to a relatively high voltage level (typically +8 volts to +12 volts). Electrons are accelerated from source region
102
to drain region
104
via the channel
122
via the channel
122
and the “hot electrons” are generated near the drain region
104
. Some of the hot electrons are injected through the relatively thin gate dielectric layer
118
and become trapped in the floating gate
106
thereby giving floating gate
106
a negatively potential.
After sufficient negative charge accumulates on floating gate
106
, the negative potential of floating gate
106
raises the threshold voltage of the stacked gate transistor and inhibits current flow through the channel
122
during a subsequent “read” mode. The magnitude of the read current is used to determine whether a memory cell has been programmed.
Conversely, to erase a flash memory device, electrons are typically driven out of the floating gate
106
by biasing the control gate
108
to a large negative voltage and biasing the source region
102
to a low positive voltage in order to produce a sufficiently large vertical electric field in the tunnel oxide. The large vertical field
136
in the tunnel oxide produces Fowler-Nordheim (F-N) tunneling of electrons stored in the floating gate
106
through the tunnel oxide into the source region
102
. Arrows
105
indicate the tunneling of the electrons from the floating gate
106
to the source region
102
. The charge removed from the floating gate
106
produces a threshold voltage shift.
For example, during erasure a relatively low positive voltage (typically from +0.5 volts to +5 volts) is applied to source electrode
114
and a relatively large negative voltage (typically from −7 volts to −13 volts) is applied to control gate electrode
120
. The voltage of the substrate electrode
126
is grounded and the drain electrode
112
is allowed to float. The vertical electric field established between the control gate
108
and the source region
102
induces electrons previously stored in floating gate
106
to pass through dielectric layer
118
and into source region
102
by way of Fowler-Nordheim tunneling.
In order to produce a sufficient electric field in the tunnel oxide, it is typically necessary to bias the control gate
108
to a large enough negative voltage such that the floating gate
106
reaches a voltage of approximately −5.5 volts. A typical potential difference V
SF
between the source region
102
and floating gate
106
is on the order of 10 volts and accordingly, when the source voltage V
S
is made less positive, the control gate voltage V
CG
should be made more negative. Once the source to floating voltage V
SF
is selected, the remaining factors are preferably constrained according to the equation:
V
FG
=&agr;
CG
(
V
CG
−&Dgr;V
T
) +&agr;
S
V
S
+&agr;
B
V
B
where:
V
FG
=the floating gate voltage;
V
CG
=the control gate voltage;
V
s
=the source voltage;
V
B
=the substrate or p-well bias;
&Dgr;V
T
=the threshold voltage difference arising from negative charge added to the floating gate as measured from the control gate;
&agr;
CG
=the capacitive coupling coefficient from the control gate to the floating gate;
&agr;
S
=the capacitive coupling coefficient between the source and the floating gate;
&agr;
B
=the capacitive coupling coefficient between the substrate or p-well and the floating gate.
As technology advances, a continuing goal throughout the industry is to increase the density of memory devices. By reducing the size of a flash EEPROM device a greater memory capacity can be achieved. As can be appreciated, the more die per wafer, the cost per die can be reduced. In addition, using higher density memory devices may provide for a reduction in the overall power consumption.
In order to increase the memory density of flash EEPROM devices, the memory cells are typically scaled down in size, for example the reduction in overall footprint of the device, is accomplished by reducing the gate length (L
GATE

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