Active solid-state devices (e.g. – transistors – solid-state diode – Regenerative type switching device – With extended latchup current level
Reexamination Certificate
2001-03-06
2003-03-04
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Regenerative type switching device
With extended latchup current level
C257S133000, C257S139000, C257S341000, C438S279000
Reexamination Certificate
active
06528826
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to depletion type MOS semiconductor devices that are suitably integrated with vertical MOSFET, and also relates to MOS power IC in which the depletion type MOS semiconductor devices are mounted, and a method of using the MOS power IC.
BACKGROUND OF THE INVENTION
Where a MOS semiconductor apparatus using a MOS semiconductor device, such as IGBT, as an output-stage semiconductor device is employed for use with an inductive load, such as an ignitor switching circuit (for intermitting current through the primary winding of an ignition coil of an automobile, for example), the IGBT suffers from oscillation of its collector voltage. To overcome this problem, the inventors of the present invention proposed that a branch of series-connected constant-current device and resistor be provided between the collector and gate of the output-stage IGBT, as disclosed in laid-open Japanese Patent Publication (Kokai) No. 9-280147.
FIG. 19
is a circuit diagram (
FIG. 1
of JP-A-9-280147) showing the configuration of the MOS semiconductor apparatus disclosed in the above publication. One of its output terminals (C) is connected to a primary winding of an ignition coil that is not illustrated. A branch in which a constant-current device
308
and a resistor
309
are connected in series is provided between the collector (c
m
) and gate (g
m
) of an output-stage IGBT
303
.
FIG. 21
shows output characteristics of this MOS power IC, wherein the horizontal axis represents the collector voltage of the IGBT, and the vertical axis represents the collector current. It is to be particularly noted that an unsaturated region of the constant-current device
308
is utilized to provide a characteristic that the collector current increases with an increase in the collector voltage, thereby to suppress oscillation of the collector voltage. In the above-identified publication, it is suggested to use a depletion type MOSFET or IGBT as the constant-current device
308
, and fabricate or build this device into a part of the output-stage IGBT
303
, but there is no specific description of such an integrated structure. It is also stated in the above publication that the constant-current device
308
may be in the form of a series power supply.
FIG. 20
is a cross-sectional view of a part of IGBT with which a depletion type and an enhancement type MOSFETs are integrated. The right-hand side portion of
FIG. 20
illustrates an output-stage IGBT
320
epitaxial wafer is generally used in which an n
+
buffer layer
322
and an n
−
drift layer
323
are laminated on a p
−
substrate
321
, and a multiplicity of IGBT units are formed in a surface layer of the n
−
drift layer
323
. On the left-hand side of
FIG. 20
, a depletion type MOSFET
340
is formed on and within a p
−
well region
333
that is formed in a surface layer of the n
−
drift layer
323
. The middle portion of
FIG. 20
illustrates an enhancement-type n-channel MOSFET formed on and within the p well region
333
, which is not related to the principle of the present invention.
To provide the depletion MOSFET
330
, an n
−
depletion region
334
, n
+
source region
335
and an n
+
drain region
336
are formed in a surface layer of the p
−
well region
333
, such that the n
+
source region
335
and n
+
drain region
336
are located on the opposite sides of the n
−
depletion region
334
. A gate electrode layer
338
is formed above the n
−
depletion region
334
with a gate insulating film
337
interposed therebetween. Source electrode
341
and drain electrode
342
are formed in contact with the n
+
source region
335
and n
+
drain region
336
, respectively, such that the source electrode
341
also contact with the gate electrode layer
338
.
With the arrangement as shown in
FIG. 20
, the constant-current device in the form of the depletion MOSFET
330
can be integrated with the IGBT on the same chip. As is understood from
FIG. 19
, the breakdown voltage of the constant-current device
308
is desirably equivalent to that of the IGBT
303
since these devices have a common output terminal (C). It is, however, extremely difficult for the lateral MOSFET formed in the p
−
well region
333
as shown in
FIG. 20
, to achieve such a high breakdown voltage as several hundreds of voltage. Accordingly, the semiconductor apparatus having the circuit configuration of
FIG. 19
must use a discrete high-voltage constant-current device or a power supply.
SUMMARY OF THE INVENTION
It is therefore an object of the present invention to provide a depletion type MOS semiconductor device that is suitably integrated with a vertical MOS type semiconductor apparatus, assuring a high breakdown voltage, and to provide a MOS power IC in which the depletion type MOS semiconductor device is mounted.
To accomplish the above object, the present invention provides a depletion type MOS semiconductor device which comprises: an n
−
drift layer; a p
−
well region formed in a surface layer of the n
−
drift layer; an n
+
emitter region formed in a surface layer of the p
−
well region; an n
−
depletion region formed in the surface layer of the p
−
well region, to extend from the n
+
emitter region to a surface layer of the n
−
drift layer; a gate electrode layer formed on a gate insulating film, over the n
−
depletion region; an emitter electrode formed in contact with surfaces of both the n
1
emitter region and the p
−
well region; and a collector electrode formed on a rear surface of the n
−
drift layer.
A p
+
collector layer may be formed on the rear surface of the n
−
drift layer, such that the collector electrode is held in contact with the p
+
collector layer.
The depletion type MOS semiconductor device constructed as described above is suitably integrated with a vertical MOSFET, or a vertical IGBT in which the collector electrode contacts with the p
+
collector layer, and exhibits a sufficiently high breakdown voltage that is equivalent to that of the MOSFET or IGBT.
In one preferred form of the invention, the p
−
well region is formed at a substantially middle portion thereof with an aperture, so as to surround the n
−
depletion region. With this arrangement, the entire area of the n
−
drift layer inside the aperture is occupied by depletion layers that spread from the p
−
well region, whereby the breakdown voltage of the device can be easily increased.
If a plurality of depletion type MOS semiconductor devices each constructed as described above are arranged in parallel with each other, the resulting MOS semiconductor apparatus provides a sufficiently large current capacity.
The p
−
well regions of the depletion type MOS semiconductor devices connected in parallel with each other may be connected with each other. In this case, the plural MOS semiconductor devices may be formed over a reduced area of the semiconductor substrate, as compared with the case where the individual devices are formed separately, and a common electrode may be used for these semiconductor devices.
A plurality of n
−
depletion regions may be formed in the n
−
drift layer surrounded by one p
−
well region. The depletion type MOS semiconductor apparatus thus constructed also provides a large current capacity.
In another preferred form of the invention, the n
−
drift layer surrounded by one p
−
well region assumes a substantially rectangular shape, and the length x of the short side of the rectangular shape is not greater than two-thirds of the thickness of the n
−
drift layer.
As will be understood from experiment results as indicated later, the breakdown voltage is undesirably reduced if the length x of the short side exceeds two-thirds of the thickness of the n
−
drift layer, probably because depletion layers that spread from opposite p
−
well re
Fijihira Tatsuhiko
Kudoh Motoi
Yoshida Kazuhiko
Fuji Electric & Co., Ltd.
Lee Calvin
Rossi & Associates
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