Density intensive non-self-aligned stacked CMOS

Details Density intensive non-self-aligned stacked CMOS Density intensive non-self-aligned stacked CMOS

1987-08-17

1989-03-21

James, Andrew J.

357 59, 357 239, H01L 2702, H01L 2904, H01L 2978

Patent

active

048148504

ABSTRACT:
A stacked CMOS structure is disclosed which uses buried N++ source and drain for the non-self-aligned bulk N-channel driver devices together with an oversized polygate on which a non-self aligned P-channel load device is made from a second layer of poly or recrystallized poly. The non-self aligned pair of stacked devices provides increased density of devices per unit area with a simple process at the cost of increased gate to source and gate to drain parasitic capacitances.

REFERENCES:
patent: 3534235 (1970-10-01), Bower et al.
patent: 4555721 (1985-11-01), Bansal et al.
Robinson, A. L., "A Fully-Self-Aligned Joint-Gate CMOS Technology", IEDM, Dec. 1983, pp. 530-533.

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