Density improvement for planar hybrid wafer scale integration

Details Density improvement for planar hybrid wafer scale integration Density improvement for planar hybrid wafer scale integration

1998-03-09

2000-04-11

Picardat, Kevin M.

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

438106, 438107, H01L 2144, H01L 2148, H01L 2150

Patent

active

060487526

ABSTRACT:
Chip-like stacks of thinned chips are mounted in wells etched into a substrate. A "chip-like" stack is a stack of chips, which in the aggregate have a height approximately equal to that of a single conventional chip. These chip-like stacks are mounted in a variety of packages. In a preferred embodiment, the stacks are mounted in wells within the substrate of an integrated circuit and the stack is provided with a patterned overlay so that all the circuit connections can be made from the upper surface of the stack. The patterned overlay is protected by a planar insulator. A plurality of substrates may be stacked, one upon the other.

REFERENCES:
patent: 5171713 (1992-12-01), Matthews
patent: 5270261 (1993-12-01), Bertin et al.
patent: 5426072 (1995-06-01), Finnila
patent: 5656553 (1997-08-01), Leas et al.

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