Dense vertical j-MOS transistor

Details Dense vertical j-MOS transistor Dense vertical j-MOS transistor

1987-09-10

1988-12-13

James, Andrew J.

357 2312, 357 2314, 357 22, H01L 2978

Patent

active

047914629

ABSTRACT:
A j-MOS structure is disclosed which operates at high current densities and provides high current handling capability. A heavily doped N+ substrate, acting as a drain, has grown on it a lightly doped N- epitaxial layer. Within the epitaxial layer are multiple N+ buried regions, each within a corresponding P+ buried region, and bisecting each of the multiple N+ regions are vertical gates extending from the upper surface of the epitaxial layer down into the N+ substrate. These gates are insulated from the epitaxial layer and substrate via a thin gate oxide layer, but are electrically connected to the multiple N+ buried regions. Between each adjacent gate pair, N+ source regions are formed on the upper surface of the epitaxial layer. The gates are connected together via a conductive layer which also electrically shorts the gates to a poly-Si contact making contact with the N+ buried regions. The N+ source regions between the gates are also electrically connected together via the conductive layer, but are insulated from the gates and P+ and N+ buried regions.

REFERENCES:
patent: 4115793 (1978-09-01), Nishizawa
patent: 4284997 (1981-08-01), Nishizawa
patent: 4546375 (1985-10-01), Blackstone et al.
patent: 4611220 (1986-09-01), MacIver
B. MacIver et al, IEEE Elect. Dev. Lettr, vol. EDL-5, No. 5, May 84, pp. 154-156 "j-MOS: A Versatile Power Field-Effect Transistor".

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