Static information storage and retrieval – Read only systems – Semiconductive
Reexamination Certificate
2003-01-23
2004-01-06
Tran, Andrew Q. (Department: 2824)
Static information storage and retrieval
Read only systems
Semiconductive
C365S103000, C365S094000
Reexamination Certificate
active
06674661
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to integrated circuits, and more particularly, to apparatuses and methods for manufacturing dense metal programmable read only memory.
2. Description of the Related Art
Semiconductor memory devices are widely used in the manufacture of digital equipment, such as microprocessor systems. To store fixed, commonly used programs, microprocessor systems generally use Read Only Memory devices or “ROMs”, such as the basic input/output system (BIOS) ROM for computer systems.
Semiconductor ROMs are typically configured as an array memory cells, wherein each individual memory cell is coupled to both a wordline and a bitline. To select a particular memory cell during a read operation, memory accessing circuitry is commonly utilized. For example, memory access circuit components typically include addressing circuitry for selecting a memory cell, wordline drivers for driving a selected wordline, sense amplifiers for amplifying the signals read from the selected memory cell, and output buffers for driving data out of the memory.
FIG. 1
is a schematic diagram of a conventional diffusion programmable ROM cell array
10
. The diffusion programmable ROM cell array
10
includes a plurality of wordlines
12
, a plurality of bitlines
14
, and a plurality of memory cells
16
, each at the intersection of a wordline
12
and a bitline
14
. It should be noted that the wordlines
12
and bitlines
14
occupy different levels of the semiconductor, and thus do not physically intersect.
In use, the wordlines
12
function as addresses for memory cells
16
, while the bitlines
14
function as the output of the cell array
10
. When manufacturing the diffusion programmable ROM cell array
10
, each memory cell
16
is programmed to output either a logical “1” or a logical “0” when the wordline
12
addressing it is activated. Generally, a wordline
12
in a diffusion ROM is activated when it is asserted high. As described in greater detail subsequently, each memory cell
16
is programmed as a “1” cell or a “0” cell during manufacturing, depending on the desired functionality of the ROM.
During a memory read operation, the ROM receives a memory address of a desired memory location within the memory cell array
10
from an address bus. The memory address, or a portion thereof, is then forwarded to an address decoder, which decodes the address and asserts one of the wordlines
12
in the memory cell array
10
high, thus activating it, all other wordlines
12
remain low. Thereafter, depending on the programming of the ROM, each bitline
14
will output either a logical “1” or “0.” In effect, by programming the various memory cell locations of the ROM, each wordline
12
can be used to select a particular binary output combination from the bitlines
14
.
FIG. 2
is a schematic diagram showing a magnified view of a conventional diffusion programmable ROM cell array
18
. The conventional diffusion programmable ROM cell array
18
includes wordlines
12
a
and
12
b
, bitlines
14
a
and
14
b
, and memory cell transistors
16
a
-
16
d.
As shown in
FIG. 2
, each memory cell of the diffusion programmable ROM memory cell array is actually a transistor
16
a
-
16
d
. Further, the gate of each memory cell transistor
16
a
-
16
d
is coupled to a wordline
12
a
/
12
b
, and a first terminal of each memory cell transistor
16
a
-
16
d
is coupled to a bitline
14
a
/
14
b
. Finally, a second terminal of each memory cell transistor
16
a
-
16
d
is coupled to ground.
Initially, a precharge circuit is used to charge each bitline
14
a
/
14
b
high, such that a logic “1” is read out from each memory cell. Thereafter, depending on the programming of the memory cell array, each bitline
14
a
/
14
b
will either remain high or be drawn low when a particular wordline
12
a
/
12
b
is activated.
For example, memory cell transistor
16
a
functions such that when wordline
12
a
is low, memory cell transistor
16
a
is shut off, and therefore bitline
14
a
maintains its state, generally high. However, when wordline
12
a
is asserted high, memory cell transistor
16
a
turns on, allowing the bitline
14
a
to be drawn to ground, thus pulling the bitline
14
a
low. Since memory cell transistor
16
a
allows the bitline
14
a
to be drawn low, it is called a “0” cell.
For a memory cell to allow the bitline to remain high when the wordline
12
is asserted, it must be programmed as a “1” cell. In a diffusion programmable ROM, the memory cell transistor
16
a
-
16
d
is simply disabled to create a “1” cell. For example, memory cell transistor
16
d
has been disabled, illustrated by its non-connection to the bitline
14
b
. Thus, regardless of the state of the wordline
12
b
, the memory cell transistor
16
d
will not pull the bitline
14
b
low, and therefore the bitline
14
b
will maintain its state, which is generally high.
FIG. 3A
is an illustration showing a conventional diffusion programmable ROM memory cell
16
a
, programmed as a “0” cell. The “0” cell
16
a
includes a wordline
12
coupled to a diffusion layer
20
, a bitline contact
22
coupling the diffusion layer
20
to a bitline
14
, and a ground diffusion wire
24
that is coupled to ground.
As stated previously, initially the bitline
14
is charged high to a logical “1.” While the wordline
12
is low, the bitline
14
remains high because the diffusion layer
20
isolates the bitline contact
22
from the ground diffusion wire
24
. However, when the wordline
12
is asserted high, the bitline
14
is pulled low because the diffusion layer
20
becomes conductive when the wordline
12
is high. Specifically, asserting the wordline
12
high charges the diffusion layer
20
and causes it to conduct, creating a connection between the bitline contact
22
and the ground diffusion wire
24
. Since the bitline
14
is coupled to the bitline contact
22
, and thus to the ground diffusion wire
24
via the diffusion layer
20
, the bitline
14
is pulled low.
FIG. 3B
is an illustration showing a conventional diffusion programmable ROM memory cell
16
d
, programmed as a “1” cell. The “1” memory cell
16
d
includes a wordline
12
, a diffusion layer
20
separated into a first portion
26
a
and a second portion
26
b
, a bitline contact
22
coupling the first portion
26
a
of the diffusion layer
20
to a bitline
14
, and a ground diffusion wire
24
coupling the second portion
26
b
of the diffusion layer
20
to ground.
Similar to the “0” cell, the “1” memory cell
16
d
initially has the bitline
14
charged high to a logical “1.” While the wordline
12
is low, the bitline
14
remains high because the diffusion layer
20
isolates the bitline contact
22
from the ground diffusion wire
24
. However, unlike the “0” cell, the “1” cell allows the bitline
14
to remain high when the wordline
12
is asserted high. Specifically, since the diffusion layer
20
is removed from around the wordline
12
, the diffusion layer
20
is not charged when the wordline
12
is asserted high, and thus, a connection is not formed between the bitline contact
22
and the ground diffusion wire
24
. Hence, the bitline
14
is never pulled low in the “1” memory cell
16
b.
FIG. 4
is an illustration showing a conventional diffusion programmable ROM cell array
30
configuration, comprising two memory cells. The conventional diffusion programmable ROM cell array
30
includes a first memory cell
32
and a second memory cell
34
. The first memory cell
32
includes a first wordline
12
a
coupled to a diffusion layer
20
, a shared bitline contact
22
coupling a bitline
14
to the diffusion layer
20
, and a first ground diffusion wire
24
a
coupling the diffusion layer
20
to ground.
The second memory cell
34
shares the diffusion layer
20
with the first memory cell
32
, and includes a second wordline
12
b
coupled to the diffusion layer
20
. The second memory cell
34
also includes the shared bitline contact
22
, which couples the bitline
14
to the diff
Artisan Components Inc.
Martine & Penilla LLP
Tran Andrew Q.
LandOfFree
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