Dense content addressable memory cell

Details Dense content addressable memory cell Dense content addressable memory cell

2003-02-26

2004-06-15

Phan, Trong (Department: 2818)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S154000, C365S156000, C365S203000

Reexamination Certificate

active

06751112

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to memory cells and more particularly relates to content addressable memory cells.
Many memory devices store and retrieve data by addressing specific memory locations. As a result, this path often becomes the limiting factor for systems that rely on fast memory access. The time required to find an item stored in memory can be reduced considerably if the stored data item can be identified for access by the content of the data itself rather than by its address. Memory that is accessed in this way is called content-addressable memory (CAM). CAM provides a performance advantage over other memory search algorithms (such as binary and tree-based searches or look-aside tag buffers) by comparing the desired information against the stored data simultaneously, often resulting in an order-of-magnitude reduction of search time.
A CAM cell is the basic circuit determining the speed, size and power consumption of a CAM system. Known CAM cells require a substantial number of transistors that consume power and require a substantial amount of area on a chip. In addition, match circuitry employed in known CAM cells requires a substantial amount of time for proper operation. This invention addresses these problems and provides a solution.
In the 0.13 micrometer and future process technologies, loss and gate leakage are becoming significant factors. Referring to FIG. 3, of U.S. Pat. No. 6,181,591 (Miyatake et al., issued Jan. 30, 2001, the “'591 patent”), node 18 will never be set to a full VDD supply voltage because NMOS transistors 16 and 17 can not pass a full VDD voltage. As a result, match transistor 25 always is partially on. Since many match transistors (e.g., 256) may be connected to the match line, the arrangement shown in the '259 patent will not work for current and future process technologies. This is particularly true at higher temperatures where the leakage current is very significant.
Another problem with current and future process technologies is gate leakage. NMOS transistor leakage is 5-10 time greater than PMOS gate leakage. If match transistor 25 shown in FIG. 3 of the '591 patent is used in connection with a four transistor SRAM cell, such as cell 11, the gate leakage of transistors 16 and 17 will make the design more difficult.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
One embodiment of the invention provides a content addressable memory cell comprising a word line, a first bit line and a second bit line. A pair of transistors is arranged to store a first bit of data at a first point and a second bit of data that is the complement of the first bit of data at a second point. A first transistor is coupled to the word line, the first bit line and the first point. A second transistor is coupled to the word line, the second bit line and the second point. A PMOS match transistor is switchable to a first state in response to a first predetermined relationship between the first and second bits and third and fourth bits transmitted on the first bit line and the second bit line and is switchable to a second state in response to a second predetermined relationship between the first and second bits and the third and fourth bits. A p-channel third transistor couples the first bit line, first point and match transistor, and a p-channel fourth transistor couples the second bit line, second point and match transistor.
By using the foregoing type of cell, the number of transistors in the CAM can be reduced and the speed of operation can be increased. The power consumption of the cell can be reduced. By using p-channel transistors for the third and fourth transistors, the need for precharging of the match transistor gate can be eliminated, because the gate of the match transistor can be charged to full VDD voltage during the BIT and BIT precharge. This guarantees that the leakage current of the transistor
40
is insignificant.
These and other advantages and novel features of the present invention, as well as details of an illustrated embodiment thereof, will be more fully understood from the following description and drawings.


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Miyatake, H. et al., “A Design For High-Speed Low-Power CMOS Fully Parallel Content-Addressable Memory Macros”,IEEE Journal of Solid-State Circuits, IEEE Inc., vol. 36, No. 6, Jun. 2001, pp. 956-968.
Noda, K. et al., “A 1.9-&mgr;m2Loadless CMOS Four-Transistor SRAM Cell in a 0.18-&mgr;m Logic Technology”, Electron Devices Meeting, 1998.IEDM '98 Technical Digest., International San Francisco, CA, 1998, pp. 643-646.
Grosspietsch, K.E., “Associative Processors and Memories: A Survey”,IEEE Micro, vol. 12, No. 3, Jun. 1, 1992, pp. 12-19.
“High Performance Static Content Addressable Memory Cell”,IBM Technical Disclosure Bulletin, IBM Corp., vol. 32, No. 3A, Aug. 1, 1989 p. 478.

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