Demultiplexor circuit

Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform

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Details

327278, 327285, 327356, 327358, H03H 1126

Patent

active

057342830

ABSTRACT:
A delay line and clock multiplying circuit are disclosed. A plurality of phase shifters impart on a reference clock successively increasing phase shifters, wherein the phase shifters have a plurality of outputs for the successively phase shifted signals. A plurality of first AND gates combine the phase shifted signals in groups to obtain a number of pulses. The pulses are then combined in a plurality of OR gates to obtain a number of pulse signals. A clock signal generator generates, from the pulse signals, mutually time delayed clock signals. A controller is arranged to control the time delay of a delay line circuit. The controller receives at least two mutually phase shifted signals from the outputs of the phase shifters and determines a delay error. The controller then generates a control signal for the delay line circuit, the magnitude of which depends upon the delay error.

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