Demultiplexing circuit for a multiplex signal

Details Demultiplexing circuit for a multiplex signal Demultiplexing circuit for a multiplex signal

1988-11-21

1989-08-29

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

H04J 302

Patent

active

048624551

ABSTRACT:
This demultiplexing circuit serves to "decode" a multiplex signal (m) formed by the formula m=ns.sub.1 +s.sub.2 from two digital signals (s.sub.1, s.sub.2) which are so redundant as to each represent an analog signal by only n amplitude levels instead of 2.sup.p maximum possible levels, where p is the respective number of bits in the digital signals, and n satisfies the relation: 2log.sub.2 n is less than or equal to 2p-1. The circuit includes an iterative array of cells each comprising an adder, a switch, and two delay elements. The output of the final stage of the iterative array provides the second digital signal. By means of inverters and shift registers, the first digital signal is derived from the carry signals of the adders.

REFERENCES:
patent: 3302008 (1967-01-01), Mitchell
patent: 4381550 (1983-04-01), Baker
patent: 4797852 (1989-01-01), Nanda

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