Demultiplexer system

Multiplex communications – Wide area network – Packet switching

Patent

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Details

3701054, H04J 306

Patent

active

049205358

ABSTRACT:
A demultiplexing circuit includes a frame synchronization circuit which simultaneously detects the occurrence of a predetermined frame synchronization pattern and the occurrence of a predetermined identification byte within the frame synchronization pattern. Since the pattern and identification bit are detected simultaneously and from the same data, the circuit is simplified and the demultiplexing is performed more quickly and efficiently.

REFERENCES:
patent: 4688218 (1987-08-01), Blinean et al.
patent: 4744081 (1988-05-01), Buckland

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