Demultiplexer for a multi-bitline bus

Details Demultiplexer for a multi-bitline bus Demultiplexer for a multi-bitline bus

1996-02-23

1998-05-12

Ton, Dang

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

370366, H04J 304

Patent

active

057517240

ABSTRACT:
A demultiplexer (10) includes an input stage (12) that receives a serial data stream having a plurality of m-bit sections at a first clock rate. The input stage converts successive n-bit portions of each m-bit section into a first n-bit parallel output at a second clock rate. An intermediary stage (14) receives the first n-bit parallel output and generates a second n-bit parallel output at the second clock rate. The first n-bit parallel output corresponds to a different portion of an m-bit section than the second n-bit parallel output. An output stage (16) receives the first n-bit parallel output from the input stage (12) and the second n-bit parallel output from the intermediary stage (14). The output stage (10) places the first n-bit parallel output onto an output bus (36) having a width of m-bitlines at an earlier instance in time than the placement of the second n-bit parallel output.

REFERENCES:
patent: 5321400 (1994-06-01), Sasaki et al.
patent: 5483540 (1996-01-01), Okamura
patent: 5546401 (1996-08-01), Lee et al.
patent: 5577039 (1996-11-01), Won et al.
patent: 5588003 (1996-12-01), Ohba et al.
PCT Search Report, PCT/US/97/02683, Jul. 7, 1997.

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