Demultiplexer

Details Demultiplexer Demultiplexer

2000-10-04

2004-09-07

Ton, Dang (Department: 2666)

Multiplex communications

Communication techniques for information carried in plural...

Combining or distributing information via time channels

C370S545000, C348S390100, C348S423100

Reexamination Certificate

active

06788711

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a demultiplexer for extracting specific individual data from among packets in which the specific individual data is stored in predetermined units.
2. Description of the Related Art
In a digital broadcast system, a transmitter side generates, multiplexes, and transmits a plurality of programs worth of transport stream (TS) packets and TS packets in which program specific information (PSI) for extracting TS packets of an intended program are stored according to the Moving Picture Experts Group Phase 2 (MPEG2) standard. The PSI is additional information of image data and audio data.
A receiver side extracts the TS packets of the program designated by a user based on the PSI and packet identification numbers of the TS packets, decodes the encoded data of the image and audio stored in the extracted TS packets, and outputs the image and audio based on the decoded data of the image and audio.
The PSI includes a region program map table (PMT), a conditional access table (CAT), a network information table (NIT), a program association table (PAT), etc.
Summarizing the disadvantages to be solved by the invention,
FIG. 1
is a schematic block configuration diagram of an example of the receiver.
This receiver
100
has a demultiplexer
10
, a first decoder
21
, a second decoder
22
, and a central processing unit (CPU)
30
.
The receiver
100
is supplied with a data train D
10
comprised by a plurality of packets. The plurality of packets have first to third packets in which individual data is stored in predetermined units stored in data regions. Predetermined units of encoded image data are stored in the data region of the first packet, while control data corresponding to the related encoded image data and/or the related first packet are stored in a header region. Predetermined units of encoded audio data are stored in the data region of the second packet, while control data corresponding to the related audio data and/or the related second packet are stored in a header region. Additional information of the encoded image data and/or the encoded audio data are stored in the data region of the third packet, while control data corresponding to the related additional information and/or the related third packet are stored in the header region.
The demultiplexer
10
is supplied with the data train D
10
, demultiplexes the first packet from the data train D
10
to extract encoded image data D
1
from the related first packet, and supplies the extracted encoded image data D
1
to the first decoder
21
.
The first decoder
21
decodes the encoded image data D
1
to generate a decoded image data D
6
and outputs the generated decoded image data D
6
to a display device
51
. The display device
51
displays the image of the decoded image data D
6
on a display screen.
Further, the demultiplexer
10
demultiplexes the second packet from the data train D
10
to extract encoded audio data D
2
from the related second packet and supplies the extracted encoded audio data D
2
to the second decoder
22
.
The second decoder
22
decodes the encoded audio data D
2
to generate decoded audio data D
7
and outputs the generated decoded audio data D
7
to a speaker
52
. The speaker
52
audio outputs the decoded audio data D
7
.
Further, the demultiplexer
10
demultiplexes the third packet from the data train D
10
and supplies an additional information D
3
from the related third packet to the CPU
30
.
The CPU
30
is a controller for overall control of the receiver
100
. This CPU
30
generates control signals C
1
to C
3
, supplies the control signal C
1
to the first decoder
21
, supplies the control signal C
2
to the second decoder
22
, and supplies the control signal C
3
to the demultiplexer
10
.
The CPU
30
controls the demultiplexer
10
to demultiplex the first packet and extract the encoded image data D
1
by the control signal C
3
based on the additional information D
3
from the demultiplexer
10
.
Further, the CPU
30
controls the demultiplexer
10
to demultiplex the second packet and extract the encoded audio data D
2
by the control signal C
3
and controls the demultiplexer
10
to demultiplex the third packet and extracts the additional information D
3
.
FIG. 2
is a schematic block diagram of an example of the configuration of the demultiplexer
10
provided in the receiver
100
of FIG.
1
.
This demultiplexer
10
has a packet demultiplexing means
19
, a first extractor
11
, a second extractor
12
, and a third extractor
13
. The packet demultiplexing means
19
and the first to third extractors
11
to
13
are controlled by the control signal C
3
from the CPU
30
.
The packet demultiplexing means
19
receives as input the data train D
10
, demultiplexes the data train D
10
into first to third packets D
11
to D
13
, supplies the first packet D
11
to the first extractor
11
, supplies the second packet D
12
to the second extractor
12
, and supplies the third packet D
13
to the third extractor
13
.
The first extractor
11
extracts the encoded image data D
1
from the first packet D
11
from the packet demultiplexing means
19
and outputs the extracted encoded image data D
1
to the first decoder
21
.
The second extractor
12
extracts the encoded audio data D
2
from the second packet D
12
from the packet demultiplexing means
19
and outputs the extracted encoded audio data D
2
to the second decoder
22
.
The third extractor
13
extracts the additional information D
3
from the third packet D
13
from the packet demultiplexing means
19
and outputs the extracted additional information D
3
to the CPU
30
.
The third extractor
13
has an extracting means
14
, a header processing means
15
, a memory
16
, and a detecting means
40
.
The extracting means
14
temporarily holds the third packet D
13
from the demultiplexing means
19
.
The header processing means
15
supplies control data D
15
stored in the header region of the third packet D
13
to the detecting means
40
.
The memory
16
stores comparison data C
16
and mask data M
16
corresponding to the control data D
15
and supplies the comparison data C
16
and the mask data M
16
to the detecting means
40
.
The detecting means
40
compares the control data D
15
from the header processing means
15
and the comparison data C
16
from the memory
16
based on the mask data M
16
and outputs detection signal D
40
to the extracting means
14
when the result of comparison indicates coincidence.
The extracting means
14
extracts the additional information D
3
from the third packet D
13
held by the related extracting means
14
based on the detection signal D
40
from the detecting means
40
and outputs the extracted additional information D
3
to the CPU
30
.
FIG. 3
is a schematic block diagram of an example of the configuration of the detecting means
40
provided in the demultiplexer
10
of FIG.
2
.
This detecting means
40
has registers
41
to
43
, a controlling means
44
, an EX-OR circuit
45
, an AND circuit
46
, and an OR circuit
47
.
The register
41
is supplied with and holds 8 bits of the control data D
15
from the header processing means
15
.
The register
42
is supplied with and holds 8 bits of the comparison data C
16
from the memory
16
.
The register
43
is supplied with and holds 8 bits of the mask data M
16
from the memory
16
.
The controlling means
44
supplies address data D
16
to the memory
16
, whereby the comparison data C
16
and the mask data M
16
corresponding to the address data D
16
are supplied from the memory
16
to the registers
42
and
43
. Further, the controlling means
44
controls a latch operation of the registers
41
to
43
.
The control data D
15
held in the register
41
and the comparison data C
16
held in the register
42
are compared for every composing bit at the EX-OR circuit
45
.
The AND logic of the output value of the EX-OR circuit
45
and the mask bit comprising the mask data M
16
held in the register
43
is found at the AND

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