Demultiplexer

Details Demultiplexer Demultiplexer

1990-09-11

1992-07-07

Olms, Douglas W.

Multiplex communications

Wide area network

Packet switching

307244, 328105, 328153, H04J 304

Patent

active

051289407

ABSTRACT:
A demultiplexer has a main circuit section obtained by connecting a plurality of 1:2 demultiplexers, each for distributing a time-divisionally multiplexed signal into tow parts, to form a tree-like arrangement, and a clock frequency divider for frequency-dividing an input clock signal to generate frequency-divided signals to be supplied to the 1:2 demultiplexers of the respective stages of the tree-like arrangement. The demultiplexer has a plurality of inverting circuits for arbitrarily inverting the frequency-divided clock signals supplied from the clock frequency divider to the respective stages of the main circuit section in units of stages.

REFERENCES:
patent: 4593390 (1986-06-01), Hildebrand et al.
patent: 4926423 (1990-05-01), Zukowski
1988 Symposium on VLSI Circuits-Digest of Technical Papers/pp. 87-88 "A 4Gb/s GaAs 16-1 Multiplexer/1-16 Demultiplexer LSI" M. Ida et al; 1988.
GaAs IC Symposium, Technical Digest 1989 pp. 317-320 "12Gbps GaAs 2-bit Multiplexer/Demultiplexer Chip Set for the Sonet STS-192 System" K. Ishida H. Wakimoto et al.

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