Demodulator for demodulating digital signal modulated by minimum

Demodulators – Frequency shift keying or minimum shift keying demodulator

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329302, 375 90, H03D 300

Patent

active

051701316

ABSTRACT:
Disclosed is a demodulation circuit for demodulating a modulated signal obtained by minimum shift keying. The demodulation circuit includes two synchronous detection circuits for detecting the modulated signal synchronously with two signals having the phases different from each other by 90.degree., respectively, a circuit for discriminating the amplitude of the output signal of one of the synchronous detection circuits to convert the output signal into a rectangular wave having two logical levels, and a circuit for sampling the rectangular wave signal in synchronization with a clock signal having a frequency corresponding to one-bit duration of the digital data. Both of two signals having the phases different by 90.degree. from each other, all of which are necessary for the synchronous detection, and the clock signal are generated based on a signal (Vt (.theta.)) obtained by multiplying the output signal of the one of the synchronous detection circuits and the output signal of the other of the synchronous detection circuits.

REFERENCES:
patent: 4359692 (1982-11-01), Ryan
patent: 4384357 (1983-05-01), deBuda et al.
Ishizuka et al., IEEE Transactions on Communications, vol. COM-28 No, 6, 850-857 (Jun. 1980).

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