Demodulators – Phase shift keying or quadrature amplitude demodulator
Reexamination Certificate
2002-01-16
2003-09-16
Choe, Henry (Department: 2817)
Demodulators
Phase shift keying or quadrature amplitude demodulator
C329S306000, C375S324000
Reexamination Certificate
active
06621332
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a device and a method for demodulating data by means of DQPSK (Differential Quadrature Phase Shift Keying) system.
2. Description of the Background Art
With the recent arrival of the IT (Information Technology) revolution represented by the Internet, the concept of home network is being turned into reality. As an example of the home network, a standard called ECHONET is now receiving attention.
ECHONET implements a network structured by utilizing home electric lines. Then, no investment is required in a new infrastructure, which is one of characteristics of ECHONET. Data transmission by this ECHONET is accomplished by employing a DQPSK modulation-demodulation system.
FIG. 1
is a block diagram schematically showing a structure of a conventional demodulator employing the DQPSK system. The conventional demodulator of the DQPSK system includes an FFT calculation unit
101
performing a fast Fourier transform (FFT) on a modulated waveform transmitted thereto to separate frequency components from the modulated waveform and thus outputting information about coordinates, on an xy plane, of a frequency to be processed, an angle calculation unit
102
performing a calculation on the xy coordinate information supplied from FFT calculation unit
101
to determine an angle value, a first register
103
holding a current angle value supplied from angle calculation unit
102
, a second register
104
holding a preceding angle value supplied from angle calculation unit
102
, a subtractor
105
subtracting the preceding angle value held in the second register
104
from the current angle value held in the first register
103
, a third register
106
holding the difference between the angle values (angular difference) supplied from subtractor
105
, an adder
107
a
adding angle “−7&pgr;/4” to the angular difference held in the third register
106
, an adder
107
b
adding angle “−5&pgr;/4” to the angular difference held in the third register
106
, an adder
107
c
adding angle “−3&pgr;/4” to the angular difference held in the third register
106
, an adder
107
d
adding angle “−1&pgr;/4” to the angular difference held in the third register
106
, an adder
107
e adding angle “+
1&pgr;/4” to the angular difference held in the third register
106
, an adder
107
f
adding angle “+3&pgr;/4” to the angular difference held in the third register
106
, an adder
107
g
adding angle “+5&pgr;/4” to the angular difference held in the third register
106
, an adder
107
h
adding angle “+7&pgr;/4” to the angular difference held in the third register
106
, a demapper
108
converting the angular difference into a 2-bit code according to the resultant sums supplied from adders
107
a
to
107
h,
and a fourth register
109
holding the code resultant from demapping by demapper
108
.
FFT calculation unit
101
separates an analogue waveform transmitted through an electric line (not shown) into frequency components to output an x coordinate value and a y coordinate value, on the xy plane, of a frequency component as a sample to be processed.
Angle calculation unit
102
performs a calculation by means of approximate expressions on the x and y coordinate values supplied from FFT calculation unit
101
to determine a vector length and an angle value of the frequency corresponding to a current sample. The angle value has a range of “0-2&pgr;”.
Synchronously with output of the angle value from angle calculation unit
102
, the first register
103
holds that angle value. At the same timing as that of holding the angle value by the first register
103
, the second register
104
holds an angle value supplied from the first register
103
. Accordingly, when the first register
103
holds an angle value of a next sample, the second register
104
holds an angle value of a preceding sample.
Subtractor
105
subtracts the angle value of the preceding sample held in the second register
104
from the angle value of the current sample held in the first register
103
to output the difference between the angle values (angular difference). The third register
106
holds and then outputs the angular difference supplied from subtractor
105
.
Angle calculation unit
102
calculates, from the x and y coordinate values, an angle value with the range of “0-2&pgr;” as described above. Accordingly, respective angle values held in the first and second registers
103
and
104
also have the range of “0-2&pgr;”. The angular difference supplied from subtractor
105
thus has a range of “−2&pgr;—2&pgr;”. Then, in order to demap the angular difference held in the third register
106
, it is necessary to determine which of nine values, i.e., “−2&pgr;, −3&pgr;/2, −&pgr;, −&pgr;/2, 0, &pgr;/2, &pgr;, 3&pgr;/2, 2&pgr;” is the angular difference.
However, in the actual demodulator, the angular difference calculated by subtractor
105
has certain variation and extent because of considerable influences of noise and distortion and the fact that the calculation is performed by means of approximate expressions. Then in consideration of the variation and extent, the determination is made as detailed below.
Determination of Angular Difference
−2&pgr;
±&pgr;/4 ( ~ −7&pgr;/4)
→ −2&pgr;
−3&pgr;/2
±&pgr;/4 (−7&pgr;/4 ~ −5&pgr;/4)
→ −3&pgr;/2
−&pgr;
±&pgr;/4 (−5&pgr;/4 ~ −3&pgr;/4)
→ −&pgr;
−&pgr;/2
±&pgr;/4 (−3&pgr;/4 ~ −&pgr;/4)
→ −&pgr;/2
0
±&pgr;/4 (−&pgr;/4 ~ +&pgr;/4)
→ 0
&pgr;/2
±&pgr;/4 (+&pgr;/4 ~ +3&pgr;/4)
→ &pgr;/2
&pgr;
±&pgr;/4 (+3&pgr;/4 ~ +5&pgr;/4)
→ &pgr;
3&pgr;/2
±&pgr;/4 (+5&pgr;/4 ~ +7&pgr;/4)
→ 3&pgr;/2
2&pgr;
±&pgr;/4 (+7&pgr;/4 ~ )
→ 2&pgr;
The determination above requires another determination as to in which region the angular difference is included. Then, a value corresponding to the boundary of each region and the angular difference undergo addition and subtraction and a sign bit of a resultant value is examined to detect a region in which the angular difference is included. Adders
107
a
to
107
h
each calculate a sum of the angular difference and the value corresponding to the boundary of each region.
For example, in order to determine whether the angular difference is greater than “+7&pgr;/4”, adder
107
a
adds “−7&pgr;/4” to the angular difference and outputs the most significant bit of the resultant sum as a sign bit. If the angular difference is greater than “+7&pgr;/4”, the resultant sum is a positive value and the sign bit supplied from adder
107
a
is “0”. On the contrary, if the angular difference is smaller than “+7&pgr;/4”, the resultant sum is a negative value and the sign bit supplied from adder
107
a
is “1”. Similarly, adders
107
b
to
107
h
make determination regarding respective boundary values “−5&pgr;/4”, “−3&pgr;/4”, “−1&pgr;/4”, “+1&pgr;/4”, “+3&pgr;/4”, “+5&pgr;/4” and “+7&pgr;/4”.
Demapper
108
inputs respective signs supplied from adders
107
a
to
107
h
as 8-bit data and classifies the angular difference from the third register
106
as any of ±n&pgr;/2 (n=0, 1, 2, 3, 4) to accomplish demapping. A relation between signs (inputs) from adders
107
a
to
107
h
and a 2-bit code after demapping is shown below. The most significant bit of an input is a sign from adder
107
a
and the least significant bit thereof is a sign from adder
107
h
.
classified
input
angular difference
demapped code
8′b0000_0000
+2&pgr;
2′b00
8′b1000_0000
+3&pgr;/2
2′b10
8′b1100_0000
+&pgr;
2′b11
8′b1110_0000
+&pgr;/2
2′b01
8′b1111_0000
0
2′b00
8′b1111_1000
+&pgr;/2
2′b10
8′b1111_1100
−&pgr;
2′b11
8&pri
Choe Henry
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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