Demodulators – Phase shift keying or quadrature amplitude demodulator
Reexamination Certificate
2000-01-27
2001-10-30
Lam, Tuan T. (Department: 2816)
Demodulators
Phase shift keying or quadrature amplitude demodulator
C329S306000
Reexamination Certificate
active
06310513
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a demodulator which is employed in a modem etc. for demodulating digitally modulated signals, and in particular, to a demodulator for demodulating signals which have been modulated by means of quadrature modulation (PSK, QAM, etc.), including an automatic quadrature error elimination circuit.
DESCRIPTION OF THE PRIOR ART
FIG. 1
is a block diagram showing an example of a conventional demodulator. The conventional demodulator of
FIG. 1
comprises multipliers
1
and
2
, a local oscillator
3
, a &pgr;/2 phase shifter
4
, A/D converters
5
and
6
, AGCs (Automatic Gain Controllers)
7
and
9
, a complex multiplier
8
, an NCO (Numerical Controlled Oscillator)
10
, an LPF (LooP Filter)
11
, a phase error detector
12
, an amplitude error detector
13
, and a signal error detector
14
.
The local oscillator
3
outputs a local oscillation signal whose frequency is almost the same as that of the carrier of a modulation signal (IF (Intermediate Frequency) signal) which is inputted to the IF input terminal of the demodulator. The &pgr;/2 phase shifter
4
shifts the phase of the local oscillation signal outputted by the local oscillator
3
by &pgr;/2. The multiplier
1
multiplies the modulation signal (IF IN) by the local oscillation signal outputted by the local oscillator
3
, and thereby a first signal component I-ch is obtained. The multiplier
2
multiplies the modulation signal (IF IN) by the &pgr;/2-shifted local oscillation signal outputted by the &pgr;/2 phase shifter
4
, and thereby a second signal component Q-ch is obtained. The first signal component I-ch outputted by the multiplier
1
is converted by the A/D converter
5
into a digital signal I-ch
1
, and the second signal component Q-ch is converted by the A/D converter
6
into a digital signal Q-ch
1
. The AGC
7
which is supplied with the digital signals I-ch
1
and Q-ch
1
corrects the amplitude difference between the digital signals I-ch
1
and Q-ch
1
, and thereby outputs digital signals I-ch
3
and Q-ch
3
in which the amplitude difference has been eliminated.
The complex multiplier
8
, which is supplied with the digital signals I-ch
3
and Q-ch
3
, corrects the digital signals I-ch
3
and Q-ch
3
by executing phase rotation using phase rotation signals Sin and Cos supplied from the NCO
10
, and thereby outputs digital signals I-ch
4
and Q-ch
4
in which the effect of the frequency difference between the carrier frequency and the local oscillation frequency of the local oscillator
3
has been eliminated. The AGC
9
adjusts the amplitudes of the digital signals I-ch
4
and Q-ch
4
based on an amplitude error signal Ad supplied from the amplitude error detector
13
so that a signal point of demodulated signals I-ch
5
and Q-ch
5
outputted by the AGC
9
will be on a normal signal point.
The signal error detector
14
, which is supplied with the demodulated signals I-ch
5
and Q-ch
5
from the AGC
9
, outputs error signals Ei and Eq and polarity signals Di and Dq. The error signals Ei and Eq outputted by the signal error detector
14
indicate that the error of the signal point of the demodulated signals I-ch
5
and Q-ch
5
in comparison with a normal signal point is (Ei, Eq). The polarity signals Di and Dq outputted by the signal error detector
14
indicate sign bits (sign binary digits) of the demodulated signals I-ch
5
and Q-ch
5
.
The amplitude error detector
13
, which is supplied with the error signals Ei (or Eq) and the polarity signal Di (or Dq) from the signal error detector
14
, calculates amplitude error of the demodulated signals I-ch
5
and Q-ch
5
and supplies the amplitude error signal Ad to the AGC
9
. The phase error detector
12
, which is supplied with the error signals Ei and Eq and the polarity signals Di and Dq from the signal error detector
14
, calculates phase error of the demodulated signals I-ch
5
and Q-ch
5
and outputs a phase error signal Pd. The phase error signal Pd outputted by the phase error detector
12
is smoothed by the LPF
11
and the smoothed phase error signal Pd
2
is supplied to the NCO
10
. The NCO
10
generates the phase rotation signals Sin and Cos using the smoothed phase error signal Pd
2
supplied from the LPF
11
, and supplies the phase rotation signals Sin and Cos to the complex multiplier
8
.
Among conventional demodulators composed of analog ICs, some demodulators executed quadrature adjustment of the output of the local oscillator
3
(i.e. correction of phase shift error of the &pgr;/2 phase shifter
4
) automatically. However, there has not been an IC capable of executing high precision quadrature adjustment which is required of a multilevel quadrature demodulator. ICs have not been designed so as to be capable of being applied to signals which have been modulated by multilevel amplitude modulation such as QAM (Quadrature Amplitude Modulation). Therefore, correction of quadrature errors has been executed manually so far.
Concretely, the quadrature adjustment for the demodulator of
FIG. 1
has been executed by slightly adjusting the phase difference of the &pgr;/2 phase shifter
4
manually. Therefore, conventional demodulators used to need extra time for the manual quadrature error correction.
Further, the phase difference of the manually adjusted &pgr;/2 phase shifter
4
tends to vary with time depending on the temperature of analog components, humidity, etc., and thus it is very difficult to guarantee the &pgr;/2 phase shift of the &pgr;/2 phase shifter
4
for the long term.
If the variations in the phase difference of the &pgr;/2 phase shifter
4
(i.e. the phase shift error) occurred, the quadrature error occurs in the demodulated signals outputted by the demodulator, thereby the characteristics of the demodulator such as the bit error rate are necessitated to be deteriorated.
SUMMARY OF THE INVENTION
It is therefore the primary object of the present invention to provide a demodulator for demodulating quadrature modulation signals, by which the quadrature error correction is executed digitally and automatically with no need of manual control and thereby deterioration of demodulation properties (bit error rate etc.) can be prevented for the long term.
Another object of the present invention is to provide a demodulation method for demodulating quadrature modulation signals, by which the quadrature error correction is executed digitally and automatically with no need of manual control and thereby deterioration of demodulation properties (bit error rate etc.) can be prevented for the long term.
In accordance with a first aspect of the present invention, there is provided a demodulator for demodulating a modulation signal (IF IN) which has been modulated by means of quadrature modulation, comprising a quasi-coherent detection means, a demodulation means, a signal error detection means, a phase error detection means, a quadrature error detection means and a quadrature error elimination means. The quasi-coherent detection means executes quasi-coherent detection to the modulation signal (IF IN) and thereby outputs quadrature components (I-ch
1
, Q-ch
1
). The demodulation means corrects amplitude errors of the quadrature components (I-ch
1
, Q-ch
1
) outputted by the quasi-coherent detection means, corrects frequency offset components and phase offset components of the quadrature components (I-ch
1
, Q-ch
1
), and thereby outputs demodulated signals (I-ch
5
, Q-ch
5
). The signal error detection means detects signal errors (Ei, Eq) and polarities (Di, Dq) of the demodulated signals (I-ch
5
, Q-ch
5
). The phase error detection means detects the phase error (Pd, Pd
1
) of the demodulated signals (I-ch
5
, Q-ch
5
) based on the signal errors (Ei, Eq) and the polarities (Di, Dq) so as to be used by the demodulation means. The quadrature error detection means detects a quadrature error (Qd) using at least the signal errors (Ei, Eq). The quadrature error elimination means executes complex multiplication to the quadrature components (I-
5
ch
1
, Q-ch
1
) outputted by the q
Lam Tuan T.
NEC Corporation
Sughrue Mion Zinn Macpeak & Seas, PLLC
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