Demodulation circuit and receiving set

Details Demodulation circuit and receiving set Demodulation circuit and receiving set

2007-03-13

2007-03-13

Kinkead, Arnold (Department: 2817)

Demodulators

Phase shift keying or quadrature amplitude demodulator

C329S311000, C329S345000

Reexamination Certificate

active

10525494

ABSTRACT:
In a sampling block40a-1, an intermediate frequency signal RIFs is sampled at a frequency of the intermediate frequency signal RIFs multiplied by “1/(m+0.25)” or “1/(m+0.75)” (m: 0 or natural number), to generate signals having phase differences “0”, “π/2”, “π”, and “3π/2”. A polarity adjustment block40a-2matches a polarity of the signal having phase difference “π” with that of the signal having phase difference “0”. Further, it matches a polarity of the signal having phase difference “3π/2” with that of the signal having phase difference “π/2”. In a signal synthesis block40a-3, the signal with phase difference “0” and the signal with phase difference “π” having phase difference “π” from each other are synthesized and held to be output as a demodulated signal PI. Further, the signal with phase difference “π/2” and the signal with phase difference “3π/2” having phase difference “π” from each other are synthesized and held to be output as a demodulated signal PQ. It is possible to provide a demodulation circuit and a receiving set that can easily obtain a good demodulated signal by a simple configuration.

REFERENCES:
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patent: 5614862 (1997-03-01), Sun
patent: 04-177946 (1992-06-01), None
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patent: 09-149091 (1997-06-01), None
patent: 09-306194 (1997-11-01), None
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